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Matthew Gelhaus  committed 2d26ba4

Fix for syntax highlighting when user-defined types, such as interfaces, are used in module port lists.

Sample SystemVerilog file used for testing:

interface my_interface1;
logic one;
logic two;

modport sys (
output one,
output two
);

endinterface

interface my_interface2;
logic one;
logic two;

modport sys (
output one,
output two
);

endinterface

module my_module
(
my_interface1 if1,
my_interface2 if2,
input logic clk,
output wire my_out

);

parameter
my_module.test_param = 23;

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File SystemVerilog.tmLanguage

 			</dict>
 			<dict>
 				<key>begin</key>
-				<string>([a-zA-Z_][a-zA-Z0-9_]*)\s+(?!intersect|and|or|throughout|within)([a-zA-Z_][a-zA-Z0-9_]*)\s*(\[(\d+)(\:(\d+))?\])?\s*(\(|$)</string>
+				<string>([a-zA-Z_][a-zA-Z0-9_]*)\s+(?!intersect|and|or|throughout|within)([a-zA-Z_][a-zA-Z0-9_]*)\s*(\[(\d+)(\:(\d+))?\])?\s*(\(|$|,)</string>
 				<key>beginCaptures</key>
 				<dict>
 					<key>1</key>
 					</dict>
 				</dict>
 				<key>end</key>
-				<string>;|=</string>
+				<string>;|=|,|$</string>
 				<key>patterns</key>
 				<array>
 					<dict>