Commits

Clams  committed 587fdd3

Fix some highlight issue + feature to show signal declaration

Highlighting:
- Fix issues related to SVA operator ##/intersect/and/or
- SVA Sequence name and `define are now part of symbol list
- Remove include file name from the symbol list (makes no sense)

New Features:
- Add simple function to display a signal declaration (from the signal name under the cursor)
- See readme for keymapping to this function

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  • Parent commits 088008c

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Files changed (4)

File SystemVerilog.tmLanguage

 				<string>meta.function.systemverilog</string>
 			</dict>
 			<dict>
+				<key>captures</key>
+				<dict>
+					<key>1</key>
+					<dict>
+						<key>name</key>
+						<string>keyword.control.systemverilog</string>
+					</dict>
+					<key>2</key>
+					<dict>
+						<key>name</key>
+						<string>entity.name.function.systemverilog</string>
+					</dict>
+				</dict>
+				<key>match</key>
+				<string>\b(sequence)\s+([a-zA-Z_][a-zA-Z0-9_]*)</string>
+				<key>name</key>
+				<string>meta.function.systemverilog</string>
+			</dict>
+			<dict>
 				<key>match</key>
 				<string>\b(automatic|cell|config|deassign|defparam|design|disable|edge|endconfig|endgenerate|endspecify|endtable|event|generate|genvar|ifnone|incdir|instance|liblist|library|localparam|parameter|macromodule|negedge|noshowcancelled|posedge|pulsestyle_onevent|pulsestyle_ondetect|scalared|showcancelled|specify|specparam|table|use|vectored)\b</string>
 				<key>name</key>
 			</dict>
 			<dict>
 				<key>match</key>
-				<string>\b(initial|always|wait|force|release|assign|always_comb|always_ff|always_latch|forever|repeat|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|randomize|with|inside|dist|clocking|cover|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|modport|matches|solve|static|assert|assume|before|expect|bind|sequence|var|cross|ref|first_match|srandom|struct|packed|final|chandle|alias|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|uwire|wait_order|triggered|randsequence|import|export|context|pure|intersect|wildcard|within|virtual|new|local|const|typedef|enum|protected|this|super|endtask|endmodule|endfunction|endprimitive|endclass|endpackage|endsequence|endprogram|endclocking|endproperty|endgroup|endinterface)\b</string>
+				<string>\b(initial|always|wait|force|release|assign|always_comb|always_ff|always_latch|forever|repeat|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|randomize|with|inside|dist|clocking|cover|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|modport|matches|solve|static|assert|assume|before|expect|bind|var|cross|ref|first_match|srandom|struct|packed|final|chandle|alias|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|uwire|wait_order|triggered|randsequence|import|export|context|pure|intersect|wildcard|within|virtual|new|local|const|typedef|enum|protected|this|super|endtask|endmodule|endfunction|endprimitive|endclass|endpackage|endsequence|endprogram|endclocking|endproperty|endgroup|endinterface)\b</string>
 				<key>name</key>
 				<string>keyword.control.systemverilog</string>
 			</dict>
 					<key>1</key>
 					<dict>
 						<key>name</key>
-						<string>constant.other.include.systemverilog</string>
+						<string>constant.other.define.systemverilog</string>
 					</dict>
 					<key>2</key>
 					<dict>
 						<key>name</key>
-						<string>entity.name.type.include.systemverilog</string>
+						<string>entity.name.type.define.systemverilog</string>
 					</dict>
 				</dict>
 				<key>match</key>
-				<string>^\s*(`include)\s+(["&lt;].*["&gt;])</string>
+				<string>^\s*(`define)\s+([a-zA-Z_][a-zA-Z0-9_]*)</string>
 				<key>name</key>
-				<string>meta.include.systemverilog</string>
+				<string>meta.define.systemverilog</string>
 			</dict>
 
 			<dict>
 			</dict>
 			<dict>
 				<key>begin</key>
-				<string>([a-zA-Z_][a-zA-Z0-9_]*)\s*(\#)</string>
+				<string>([a-zA-Z_][a-zA-Z0-9_]*)\s*(#)[^#]</string>
 				<key>beginCaptures</key>
 				<dict>
 					<key>1</key>
 			</dict>
 			<dict>
 				<key>begin</key>
-				<string>([a-zA-Z_][a-zA-Z0-9_]*)\s+([a-zA-Z_][a-zA-Z0-9_]*)\s*(\[(\d+)(\:(\d+))?\])?\s*(\(|$)</string>
+				<string>([a-zA-Z_][a-zA-Z0-9_]*)\s+(?!intersect|and|or|throughout|within)([a-zA-Z_][a-zA-Z0-9_]*)\s*(\[(\d+)(\:(\d+))?\])?\s*(\(|$)</string>
 				<key>beginCaptures</key>
 				<dict>
 					<key>1</key>

File package-metadata.json

-{"url": "https://bitbucket.org/Clams/sublimesystemverilog", "version": "2012.07.04.18.10.13", "description": "Support for systemVerilog syntaxHighlighting + some snippets.\r\nUsed Textmate verilog bundle to start"}
+Sublime Text SystemVerilog Package
+==================================
+
+
+Description
+-----------
+
+Syntax Highlighting:
+ - SystemVerilog
+ - UCF (Xilinx Constraint file)
+
+Various snippets: module, class, if/else, case, ...
+
+Features:
+ - Show signal declaration in status bar
+ - hopefully more to come :P
+
+
+Keymapping example
+------------------
+
+To map key to the different feature, simply add the following to your user .sublime-keymap file:
+
+    {
+        "keys": ["f10"], "command": "verilog_type",
+        "context":
+		[
+			{ "key": "num_selections", "operator": "equal", "operand": 1 },
+			{ "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
+		]
+    }
+
+import sublime, sublime_plugin
+import re, string, os
+
+
+class VerilogTypeCommand(sublime_plugin.TextCommand):
+
+    def run(self,edit):
+        if len(self.view.sel())==0 : return;
+        region = self.view.sel()[0]
+        # If nothing is selected expand selction to word
+        if region.empty() : region = self.view.word(region);
+        s = self.get_type(self.view.substr(region))
+        sublime.status_message(s)
+
+    def get_type(self,var_name):
+        #Find first line containing the variable name
+        r = self.view.find('\\b'+var_name+'\\b',0)
+        if r==None : return;
+        r = self.view.line(r)
+        # Extract type
+        return self.view.substr(r)