First off, I want to thank you for the awesome package. It has filled such a gap in my HDL development process.
I'm seeing a lot of hangs recently on my top module.
Here are a few examples: 1) When I try to write "always" it hangs for a several minutes after I type "a". 2) I've also seen it hang sometimes when I highlight a net. 3) When using the "Veilog: Instantiate Module" helper it hangs for several mintutes after i choose which module to instantiate.
All these features seem to work fine when I'm working in other modules. Do you have any recommendations on how to troubleshoot this problem?