Issue #4 new
repo owner created an issue

Add command to align code properly (module instantiation, signal declaration, ...)

Comments (14)

  1. Clams reporter

    Start support in commit 52 (version 1.4.0): module instantiation and module port declaration. TODO: signal declaration, non-blocking assignement, case()

  2. Clams reporter

    Update in 0dceb82 (version 1.10.0) to support assignment (blocking/non blocking), case and struct assign. TODO: global reindent with begin end, one line if/for/while

  3. Clams reporter

    Add reindent command in 5368d10.


    • add option to enforce some indent style (K&R /1TBS / GNU)
    • add beautify command that would call all the different align/reindent command
  4. Clams reporter

    Biggest part of the work done. Some improvement todo:

    • ternary operator " ? : " alignement on multiple lines
    • alignment on = for assign split on multiple lines
    • alignment between multiple affectation inside function/task
    • Alignement on { in structure affectation when not at end of line
  5. Clams reporter

    By adding the argument cmd="reindent" to the verilog_align command. The keybinding example in the readme is alt+shift+a. This was broken when I rework the beautifier, but should be ok now

  6. Nico Lugil

    Pretty basic question: what is the difference between reindent and code alignment. I have some code that looks weird after doing reindent, but is ok after alignment.

  7. Clams reporter

    Reindent will not perform special alignement on port/signal declaration, or assignment or any stuff like that, it only look at the code indentation.

  8. mrvkino

    Could it be possible for the alignement function to skip (ignore) the `ifdef, `ifndef, `else, `endif. Right now it causes indentation/alignement problem in my port declaration.

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