1. Clams
  2. SublimeSystemVerilog

Source

SublimeSystemVerilog /

Filename Size Date modified Message
debug
messages
Snippets
test
verilogutil
114 B
Fix issue 82 (Alignment of system function in port declaration)
4.7 KB
Added tag 2.10.0 for changeset 9bb97741e2a0
1.3 KB
New feature: find undeclared signals in a module
200 B
Improved autocompletion:
1.3 KB
Version 1.12.0 : Add 3 new features (reconnect, find instances, find unused signals)
11.3 KB
Add a license
653 B
Add more option to the module instantiation function:
734 B
Minor highlighting update:
3.9 KB
Tooltips now displayed onHover (new feature in ST 3116)
24.5 KB
Fix issue #114 (FSM template with type defined locally)
45.1 KB
Add keyword unique 0 (fix issue #75)
1.5 KB
Improve module autoconnection
0 B
fix #35 #38: add tests, logger; add __init__ for import mechanism
178 B
Add more option to the module instantiation function:
3.6 KB
Tooltips now displayed onHover (new feature in ST 3116)
4.2 KB
New feature: find undeclared signals in a module
7.9 KB
Fix issue #103 (Highlight of wire with userdefined type)
4.4 KB
Fix Issue #25 (UCF comment support for //)
581 B
Add UCF support
3.8 KB
Fix regression on package completion (introduced in 2.8.2)
49.1 KB
Fix alignement issue with multi-dimensionnal unpacked array
36.1 KB
Fix issue #109 : Module instantiation file list can use unsaved project files (regression introduce in 2.9.0
42.2 KB
Tooltips now displayed onHover (new feature in ST 3116)

Sublime Text SystemVerilog Package

Description

Syntax Highlighting:

  • SystemVerilog / Verilog
  • UCF (Xilinx Constraint file)

Note: the default color scheme (Monokai) is missing a lot of scope, and might not give the best results. You can try my personal variation of Sunburst : https://bitbucket.org/Clams/sublimesystemverilog/downloads/Sunburst2.tmTheme

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Goto declaration : move cursor to the declaration of the selected signal
  • Goto driver : select a signal a go to the driver (port, assignement, connection)
  • Find Instances: find all instance of a module inside a project
  • Show hierarchy of a module (all its sub-module)

Code Completion :

  • Smart Autocompletion: method for standard type, field for struct/interface/class, system task, ...
  • Smart snippet for always, case
  • 'begin end' macro to surround a text by begin/end (cf Keymapping section to see how to use it)
  • Various Snippets (module, interface, class, for, ...)
  • Insert template for FSM

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection
  • Reconnect: remove connection to deleted port, add connection to new port
  • Toggle .* in module binding (similar to the auto-star feature of Emacs verilog-mode)

Code Alignement:

  • Reindent
  • Align module port
  • Align signal declaration
  • Align module instantiation
  • Align assignement

Linting:

  • Find/Remove all unused signals
  • List all undeclared signals

Configuration

To see all existing configuration option, go to Preferences->Package Settings->SystemVerilog->Settings (Default).

To edit settings open the Settings (User), and add parameter with the value you want.

Detail documentation

For a detail documentation on the different features, check online documentation: http://sv-doc.readthedocs.org/en/latest .

Keymapping example

To map key to the different feature, simply add the following to your user .sublime-keymap file:

{
    "keys": ["f10"], "command": "verilog_type",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f10"], "command": "verilog_module_inst",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+f10"], "command": "verilog_toggle_dot_star",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+a"], "command": "verilog_align",
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["alt+shift+a"], "command": "verilog_align", "args":{"cmd":"reindent"},
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f12"], "command": "verilog_goto_driver",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["shift+f12"], "command": "verilog_goto_declaration",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
// Begin/End
{
    "keys": ["ctrl+'"],
    "command": "insert_snippet", "args": {"contents": "begin\n\t$0\nend"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": true, "match_all": true }]
},
{
    "keys": ["ctrl+'"],
    "command": "run_macro_file",
    "args": {"file": "Packages/SystemVerilog/beginend.sublime-macro"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": false, "match_all": true }]
},