Source

SublimeSystemVerilog /

Filename Size Date modified Message
debug
messages
test
verilogutil
102 B
Module instance: add option to declare parameter/localparam
1.1 KB
Add reindent feature (first basic version)
200 B
Improved autocompletion:
1.3 KB
Version 1.12.0 : Add 3 new features (reconnect, find instances, find unused signals)
11.0 KB
Add a license
653 B
Add more option to the module instantiation function:
734 B
Minor highlighting update:
3.2 KB
Show signal info can now use the tooltip
43.8 KB
removed change that was supposed to be deleted before previous commit
1.4 KB
Improve module autoconnection
0 B
fix #35 #38: add tests, logger; add __init__ for import mechanism
179 B
Fix snippet indentation + improve highlight on typedef, bind, ...
178 B
Add more option to the module instantiation function:
219 B
Fix snippet indentation + improve highlight on typedef, bind, ...
239 B
Fix snippet indentation + improve highlight on typedef, bind, ...
1.0 KB
Fix snippet indentation + improve highlight on typedef, bind, ...
326 B
SystemVerilog 1.1.3 Changelog:
197 B
Fix completion of word starting by u (was not taking the default auto-completion...)
233 B
Improve module autoconnection
215 B
Fix snippet indentation + improve highlight on typedef, bind, ...
212 B
Fix snippet indentation + improve highlight on typedef, bind, ...
256 B
Fix snippet indentation + improve highlight on typedef, bind, ...
219 B
Small update of autocompletion and misc. bug fixes
2.0 KB
Tooltip: better handling of enum and highlight operator : and #
317 B
Small update of autocompletion and misc. bug fixes
208 B
Small update of autocompletion and misc. bug fixes
3.8 KB
Show signal info can now use the tooltip
199 B
Add snippets for always block with reset active high
2.2 KB
Fix some snippets and always includes description
4.3 KB
Fix Issue #25 (UCF comment support for //)
581 B
Add UCF support
32.2 KB
Bug fixes for alignement
34.0 KB
Fix some snippets and always includes description
27.1 KB
Tooltip: better handling of enum and highlight operator : and #
23.8 KB
Fix some snippets and always includes description

Sublime Text SystemVerilog Package

Description

Syntax Highlighting:

  • SystemVerilog / Verilog
  • UCF (Xilinx Constraint file)

Code Navigation:

  • Show signal declaration in tooltip or status bar
  • Goto declaration : move cursor to the declaration of the selected signal
  • Goto driver : select a signal a go to the driver (port, assignement, connection)
  • Find Instances: find all instance of a module inside a project
  • Show hierarchy of a module (all its sub-module)

Code Completion :

  • Smart Autocompletion: method for standard type, field for struct/interface, system task, ...
  • Smart snippet for always, case
  • 'begin end' macro to surround a text by begin/end (cf Keymapping section to see how to use it)
  • Various Snippets (module, interface, class, for, ...)
  • Insert template for FSM
  • Find/Remove all unused signals

Module Instance helper:

  • Instantiation: Select a module from a list and create instantiation and connection
  • Reconnect: remove connection to deleted port, add connection to new port
  • Toggle .* in module binding (similar to the auto-star feature of Emacs verilog-mode)

Code Alignement:

  • Reindent
  • Align module port
  • Align signal declaration
  • Align module instantiation
  • Align assignement

Configuration

To see all existing configuration option, go to Preferences->Package Settings->SystemVerilog->Settings (Default).

To edit settings open the Settings (User), and add parameter with the value you want.

Detail documentation

For a detail documentation on the different features, check online documentation: http://sv-doc.readthedocs.org/en/latest .

Keymapping example

To map key to the different feature, simply add the following to your user .sublime-keymap file:

{
    "keys": ["f10"], "command": "verilog_type",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f10"], "command": "verilog_module_inst",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+shift+f10"], "command": "verilog_toggle_dot_star",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog meta.module.inst"}
    ]
},
{
    "keys": ["ctrl+shift+a"], "command": "verilog_align",
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["alt+shift+a"], "command": "verilog_align", "args":{"cmd":"reindent"},
    "context":
    [
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["ctrl+f12"], "command": "verilog_goto_driver",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
{
    "keys": ["shift+f12"], "command": "verilog_goto_declaration",
    "context":
    [
        { "key": "num_selections", "operator": "equal", "operand": 1 },
        { "key": "selector", "operator": "equal", "operand": "source.systemverilog"}
    ]
},
// Begin/End
{
    "keys": ["ctrl+'"],
    "command": "insert_snippet", "args": {"contents": "begin\n\t$0\nend"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": true, "match_all": true }]
},
{
    "keys": ["ctrl+'"],
    "command": "run_macro_file",
    "args": {"file": "Packages/SystemVerilog/beginend.sublime-macro"},
    "context": [{ "key": "selection_empty", "operator": "equal", "operand": false, "match_all": true }]
},