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Created by
Alex Hogen
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/*************************************************************************//**
* \file ripple_carry_adder.sv
* \brief Creates a ripple carry adder at the bit width specified internally.
*
* \author Alexander Hogen
* \date 10/7/2016
*
* DISCLAIMER:
*
* This code, in any raw, compiled, simulated, or synthesized form, is provided to
* you and/or the end-user "AS IS" without any warranties or support.
*
* There is no warranty for the code, to the extent permitted by applicable law.
* Except when otherwise stated in writing the copyright holders and/or other parties
* provide the code "AS IS" without warranty of any kind, either expressed or
* implied, including, but not limited to, the implied warranties of merchantability
* and fitness for a particular purpose. The entire risk as to the quality and
* performance of the code is with you. Should the code prove defective, you assume
* the cost of all necessary servicing, repair, or correction.
*
* In no event unless required by applicable law or agreed to in writing will any
* copyright holder, or any other party who modifies and/or conveys the code as
* permitted above, be liable to you for damages, including any general, special,
* incidental, or consequential damages arising out of the use or inability to use
* the code (including but not limited to loss of data or data being rendered
* inaccurate or losses sustained by you or third parties or a failure of the code
* to operate with any other programs), even if such holder or other party has been
* advised of the possibility of such damages.
*
* By using this code in any way, you agree to the above statements.
*
*****************************************************************************/
module ripple_carry_adder (
input [BW:0] a,
input [BW:0] b,
output logic [BW + 1:0] out
);
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
parameter DESIRED_BIT_WIDTH = 6; // <===== CHANGE THIS to fit your needs!
parameter BW = DESIRED_BIT_WIDTH -1;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// Dataflow model of a half adder
module half_adder (
input a,
input b,
output logic sum,
output logic cout
);
always_comb
begin
sum = (a ^ b);
cout = (a & b);
end
endmodule
// Dataflow model of a full adder
module full_adder (
input a,
input b,
input cin,
output logic sum,
output logic cout
);
always_comb
begin
sum = a ^ (b ^ c);
cout = (a & b) | (a & c) | (b & c);
end
endmodule
/*****************************************************************************
* Internal Wires and Register Declarations *
*****************************************************************************/
wire [BW:0] carry;
wire [BW:0] sum;
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign out = { carry[BW], sum[BW:0] };
// Instantiate a single half adder module, for the first adder in the chain.
half_adder HA (
.a ( a[0] ),
.b ( b[0] ),
.sum ( sum[0] ),
.cout ( carry[0] )
);
// Use a generate block to automatically create full adders to perform the rest
// of the additions.
genvar i;
generate
for ( i = 1; i <= BW; i = i + 1) begin: FullAdderGenerate
full_adder FA (
.a ( a[i] ),
.b ( b[i] ),
.cin ( carry[i-1] ),
.sum ( sum[i] ),
.cout ( carry[i] )
);
end
endgenerate
endmodule
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