Commits

Martin Vejnár committed 0fbd63b

Added a basic output logic controllable from nios.

Comments (0)

Files changed (6)

firmware-board/omicron_analyzer.qsf

 set_global_assignment -name VERILOG_FILE omicron_analyzer.v
 set_global_assignment -name QIP_FILE omicron_analyzer_sopc.qip
 set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name VERILOG_FILE totem_port.v
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

firmware-board/omicron_analyzer.v

 	
 reg[15:0] sample_in_sync1;
 reg[15:0] sample_in_sync2;
+reg[15:0] sig;
 
 wire sopc_clock = clk_50;
 wire sampling_clock = clk_50;
 always @(posedge sampling_clock) begin
 	sample_in_sync1 <= sig_n;
 	sample_in_sync2 <= sample_in_sync1;
+	sig <= ~sample_in_sync2;
 end
 
 wire sopc_reset_n = rst_n;
 
-sfl sfl_0(
+/*sfl sfl_0(
 	.noe_in(1'b0)
-	);
+	);*/
 
 assign vdd5v = 1'b0;
 
-assign outl = 16'h0000;
-assign outh = 16'h0000;
+reg[15:13] port_oe;
+reg[15:13] port_out;
+totem_port totem_port_0(
+	.clk(sopc_clock),
+	.reset(!rst_n),
+	.in(port_out),
+	.oe(port_oe),
+	.outl(outl),
+	.outh(outh)
+);
+
+wire[15:0] port_sopc_oe;
+wire[15:0] port_sopc_out;
+
+always @(*) begin
+	port_oe = port_sopc_oe;
+	port_out = port_sopc_out;
+end
 
 wire sample_strobe;
 omicron_analyzer_sopc sopc_0
 	.cts_n_to_the_uart_0                        (uart0_cts_n),
 	.rts_n_from_the_uart_0                      (uart0_rtr_n),
 
+	.in_port_to_the_sig_pin                     (sig),
+	.out_port_from_the_sig_output_enable        (port_sopc_oe),
+	.out_port_from_the_sig_port                 (port_sopc_out),
+
 	.out_port_from_the_leds                     (led),
 	
 	.timeout_pulse_from_the_timer               (sample_strobe),
 
-	.sample_in_to_the_sample_source_0           (sample_in_sync2),
+	.sample_in_to_the_sample_source_0           (sig),
 	.sample_strobe_to_the_sample_source_0       (sample_strobe),
 
 	.zs_addr_from_the_sdram                     (dram_addr),

firmware-board/omicron_analyzer_sopc.sopc

          type = "int";
       }
    }
-   element sysid.control_slave
-   {
-      datum baseAddress
-      {
-         value = "33587392";
-         type = "long";
-      }
-   }
-   element sample_writer_0.control_slave
-   {
-      datum baseAddress
-      {
-         value = "33587360";
-         type = "long";
-      }
-   }
    element sample_source_0.control_slave
    {
       datum baseAddress
          type = "long";
       }
    }
+   element sysid.control_slave
+   {
+      datum baseAddress
+      {
+         value = "33587472";
+         type = "long";
+      }
+   }
    element sample_compressor_0.control_slave
    {
       datum baseAddress
       {
-         value = "33587376";
+         value = "33587440";
+         type = "long";
+      }
+   }
+   element sample_writer_0.control_slave
+   {
+      datum baseAddress
+      {
+         value = "33587424";
          type = "long";
       }
    }
          type = "int";
       }
    }
+   element sig_port.s1
+   {
+      datum baseAddress
+      {
+         value = "33587360";
+         type = "long";
+      }
+   }
+   element sig_output_enable.s1
+   {
+      datum baseAddress
+      {
+         value = "33587392";
+         type = "long";
+      }
+   }
+   element sig_pin.s1
+   {
+      datum baseAddress
+      {
+         value = "33587456";
+         type = "long";
+      }
+   }
+   element uart_1.s1
+   {
+      datum baseAddress
+      {
+         value = "33587200";
+         type = "long";
+      }
+   }
    element leds.s1
    {
       datum baseAddress
          type = "long";
       }
    }
+   element ram.s1
+   {
+      datum baseAddress
+      {
+         value = "33570816";
+         type = "long";
+      }
+   }
+   element uart_0.s1
+   {
+      datum baseAddress
+      {
+         value = "33587328";
+         type = "long";
+      }
+   }
    element sdram.s1
    {
       datum _lockedAddress
          type = "long";
       }
    }
-   element ram.s1
-   {
-      datum baseAddress
-      {
-         value = "33570816";
-         type = "long";
-      }
-   }
-   element uart_0.s1
-   {
-      datum baseAddress
-      {
-         value = "33587328";
-         type = "long";
-      }
-   }
-   element uart_1.s1
-   {
-      datum baseAddress
-      {
-         value = "33587200";
-         type = "long";
-      }
-   }
    element sample_compressor_0
    {
       datum _sortIndex
          type = "String";
       }
    }
+   element sig_output_enable
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+   }
+   element sig_pin
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+   }
+   element sig_port
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+   }
    element sysid
    {
       datum _sortIndex
  <parameter name="maxAdditionalLatency" value="0" />
  <parameter name="projectName">omicron_analyzer.qpf</parameter>
  <parameter name="sopcBorderPoints" value="true" />
- <parameter name="systemHash" value="-6639330232" />
- <parameter name="timeStamp" value="1298493068079" />
+ <parameter name="systemHash" value="7186759500" />
+ <parameter name="timeStamp" value="1298495572670" />
  <module kind="clock_source" version="10.1" enabled="1" name="clk_0">
   <parameter name="clockFrequency" value="50000000" />
   <parameter name="clockFrequencyKnown" value="true" />
   <parameter name="dcache_numTCDM" value="_0" />
   <parameter name="dcache_lineSize" value="_32" />
   <parameter name="dcache_bursts" value="false" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x0' end='0x2000000' /><slave name='ram.s1' start='0x2004000' end='0x2008000' /><slave name='uart_1.s1' start='0x2008000' end='0x2008020' /><slave name='leds.s1' start='0x2008020' end='0x2008040' /><slave name='timer.s1' start='0x2008040' end='0x2008060' /><slave name='sample_source_0.control_slave' start='0x2008060' end='0x2008080' /><slave name='uart_0.s1' start='0x2008080' end='0x20080A0' /><slave name='sample_writer_0.control_slave' start='0x20080A0' end='0x20080B0' /><slave name='sample_compressor_0.control_slave' start='0x20080B0' end='0x20080C0' /><slave name='sysid.control_slave' start='0x20080C0' end='0x20080C8' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sdram.s1' start='0x0' end='0x2000000' /><slave name='ram.s1' start='0x2004000' end='0x2008000' /><slave name='uart_1.s1' start='0x2008000' end='0x2008020' /><slave name='leds.s1' start='0x2008020' end='0x2008040' /><slave name='timer.s1' start='0x2008040' end='0x2008060' /><slave name='sample_source_0.control_slave' start='0x2008060' end='0x2008080' /><slave name='uart_0.s1' start='0x2008080' end='0x20080A0' /><slave name='sig_port.s1' start='0x20080A0' end='0x20080C0' /><slave name='sig_output_enable.s1' start='0x20080C0' end='0x20080E0' /><slave name='sample_writer_0.control_slave' start='0x20080E0' end='0x20080F0' /><slave name='sample_compressor_0.control_slave' start='0x20080F0' end='0x2008100' /><slave name='sig_pin.s1' start='0x2008100' end='0x2008110' /><slave name='sysid.control_slave' start='0x2008110' end='0x2008118' /></address-map>]]></parameter>
   <parameter name="dataAddrWidth" value="26" />
   <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
   <parameter name="cpuReset" value="false" />
   <parameter name="useEopRegister" value="false" />
   <parameter name="useRelativePathForSimFile" value="false" />
  </module>
+ <module kind="altera_avalon_pio" version="10.1" enabled="1" name="sig_pin">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Input" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="16" />
+ </module>
+ <module kind="altera_avalon_pio" version="10.1" enabled="1" name="sig_port">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="true" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="16" />
+ </module>
+ <module
+   kind="altera_avalon_pio"
+   version="10.1"
+   enabled="1"
+   name="sig_output_enable">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="true" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="clockRate" value="50000000" />
+  <parameter name="direction" value="Output" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="false" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="16" />
+ </module>
  <connection
    kind="avalon"
    version="10.1"
    start="cpu.data_master"
    end="sysid.control_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x020080c0" />
+  <parameter name="baseAddress" value="0x02008110" />
  </connection>
  <connection kind="avalon" version="10.1" start="cpu.data_master" end="uart_1.s1">
   <parameter name="arbitrationPriority" value="1" />
    start="cpu.data_master"
    end="sample_writer_0.control_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x020080a0" />
+  <parameter name="baseAddress" value="0x020080e0" />
  </connection>
  <connection
    kind="avalon"
    start="cpu.data_master"
    end="sample_compressor_0.control_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x020080b0" />
+  <parameter name="baseAddress" value="0x020080f0" />
  </connection>
  <connection kind="clock" version="10.1" start="clk_0.clk" end="cpu.clk" />
  <connection kind="clock" version="10.1" start="clk_0.clk" end="ram.clk1" />
  <connection kind="interrupt" version="10.1" start="cpu.d_irq" end="uart_0.irq">
   <parameter name="irqNumber" value="2" />
  </connection>
+ <connection kind="clock" version="10.1" start="clk_0.clk" end="sig_pin.clk" />
+ <connection kind="avalon" version="10.1" start="cpu.data_master" end="sig_pin.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x02008100" />
+ </connection>
+ <connection kind="clock" version="10.1" start="clk_0.clk" end="sig_port.clk" />
+ <connection
+   kind="avalon"
+   version="10.1"
+   start="cpu.data_master"
+   end="sig_port.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x020080a0" />
+ </connection>
+ <connection
+   kind="clock"
+   version="10.1"
+   start="clk_0.clk"
+   end="sig_output_enable.clk" />
+ <connection
+   kind="avalon"
+   version="10.1"
+   start="cpu.data_master"
+   end="sig_output_enable.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x020080c0" />
+ </connection>
 </system>

firmware-board/software/test/hello_world_small.c

 
 void memory_check(void);
 
+void print_hex(uint8_t value)
+{
+	static char const digits[] = "0123456789abcdef";
+
+	uart_write(digits[value >> 4]);
+	uart_write(digits[value & 0xf]);
+}
+
+void print_hex_int(unsigned value)
+{
+	print_hex(value >> 24);
+	print_hex(value >> 16);
+	print_hex(value >> 8);
+	print_hex(value);
+}
+
 void process_text(unsigned char ch)
 {
 	switch (ch)
 	case ' ':
 		stop_sampling();
 		break;
+	case 'p':
+		print_hex_int(IORD_ALTERA_AVALON_PIO_DATA(SIG_PIN_BASE));
+		uart_write('\n');
+		break;
+	case '1':
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(SIG_PORT_BASE, (1<<13));
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<13));
+		break;
+	case '2':
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(SIG_PORT_BASE, (1<<14));
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<14));
+		break;
+	case '3':
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(SIG_PORT_BASE, (1<<15));
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<15));
+		break;
+	case '4':
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<13));
+		break;
+	case '5':
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<14));
+		break;
+	case '6':
+		IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<15));
+		break;
+	case '7':
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_PORT_BASE, (1<<13));
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<13));
+		break;
+	case '8':
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_PORT_BASE, (1<<14));
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<14));
+		break;
+	case '9':
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_PORT_BASE, (1<<15));
+		IOWR_ALTERA_AVALON_PIO_SET_BITS(SIG_OUTPUT_ENABLE_BASE, (1<<15));
+		break;
 	default:
 		uart_write(ch + 1);
 	}

firmware-board/software/test_bsp/settings.bsp

 <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
         <BspType>hal</BspType>
         <BspVersion>default</BspVersion>
-        <BspGeneratedTimeStamp>Feb 23, 2011 9:45:49 PM</BspGeneratedTimeStamp>
-        <BspGeneratedUnixTimeStamp>1298493949991</BspGeneratedUnixTimeStamp>
+        <BspGeneratedTimeStamp>Feb 26, 2011 4:32:51 PM</BspGeneratedTimeStamp>
+        <BspGeneratedUnixTimeStamp>1298734372028</BspGeneratedUnixTimeStamp>
         <BspGeneratedLocation>X:\checkouts\omicron_analyzer\firmware-board\software\test_bsp</BspGeneratedLocation>
         <BspSettingsFile>settings.bsp</BspSettingsFile>
         <SopcDesignFile>..\..\omicron_analyzer_sopc.sopcinfo</SopcDesignFile>
                 <attributes>printable</attributes>
         </MemoryMap>
         <MemoryMap>
+                <slaveDescriptor>sig_port</slaveDescriptor>
+                <addressRange>0x020080A0 - 0x020080BF</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>sig_output_enable</slaveDescriptor>
+                <addressRange>0x020080C0 - 0x020080DF</addressRange>
+                <addressSpan>32</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
                 <slaveDescriptor>sample_writer_0</slaveDescriptor>
-                <addressRange>0x020080A0 - 0x020080AF</addressRange>
+                <addressRange>0x020080E0 - 0x020080EF</addressRange>
                 <addressSpan>16</addressSpan>
                 <attributes/>
         </MemoryMap>
         <MemoryMap>
                 <slaveDescriptor>sample_compressor_0</slaveDescriptor>
-                <addressRange>0x020080B0 - 0x020080BF</addressRange>
+                <addressRange>0x020080F0 - 0x020080FF</addressRange>
+                <addressSpan>16</addressSpan>
+                <attributes/>
+        </MemoryMap>
+        <MemoryMap>
+                <slaveDescriptor>sig_pin</slaveDescriptor>
+                <addressRange>0x02008100 - 0x0200810F</addressRange>
                 <addressSpan>16</addressSpan>
                 <attributes/>
         </MemoryMap>
         <MemoryMap>
                 <slaveDescriptor>sysid</slaveDescriptor>
-                <addressRange>0x020080C0 - 0x020080C7</addressRange>
+                <addressRange>0x02008110 - 0x02008117</addressRange>
                 <addressSpan>8</addressSpan>
                 <attributes/>
         </MemoryMap>
         </DriverPackageInfo>
         <DriverPackageInfo>
                 <name>altera_avalon_uart_driver</name>
+                <version>default</version>
+                <moduleName>uart_0</moduleName>
+        </DriverPackageInfo>
+        <DriverPackageInfo>
+                <name>altera_avalon_uart_driver</name>
                 <version>10.1</version>
                 <moduleName>uart_1</moduleName>
         </DriverPackageInfo>
         </DriverPackageInfo>
         <DriverPackageInfo>
                 <name>altera_avalon_pio_driver</name>
+                <version>default</version>
+                <moduleName>sig_port</moduleName>
+        </DriverPackageInfo>
+        <DriverPackageInfo>
+                <name>altera_avalon_pio_driver</name>
+                <version>default</version>
+                <moduleName>sig_pin</moduleName>
+        </DriverPackageInfo>
+        <DriverPackageInfo>
+                <name>altera_avalon_pio_driver</name>
+                <version>default</version>
+                <moduleName>sig_output_enable</moduleName>
+        </DriverPackageInfo>
+        <DriverPackageInfo>
+                <name>altera_avalon_pio_driver</name>
                 <version>10.1</version>
                 <moduleName>leds</moduleName>
         </DriverPackageInfo>
-        <DriverPackageInfo>
-                <name>altera_avalon_uart_driver</name>
-                <version>default</version>
-                <moduleName>uart_0</moduleName>
-        </DriverPackageInfo>
 </sch:Settings>

firmware-board/totem_port.v

+module totem_port #(
+	parameter width = 16
+)(
+	input clk,
+	input reset,
+	input[width-1:0] in,
+	input[width-1:0] oe,
+	output reg[width-1:0] outl,
+	output reg[width-1:0] outh
+);
+
+generate
+genvar i;
+for (i = 0; i < width; i = i + 1)
+	begin : b
+		always @(posedge clk or posedge reset) begin
+			if (reset) begin
+				outl[i] <= 1'b0;
+				outh[i] <= 1'b0;
+			end else begin
+				outl[i] <= oe[i] && !outh[i] && in[i] == 1'b0;
+				outh[i] <= oe[i] && !outl[i] && in[i] == 1'b1;
+			end
+		end
+	end
+endgenerate
+
+endmodule