Commits

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Author Commit Message Labels Comments Date
Martin Vejnár
Added a sketch of the plugin for Asix Sigma.
Martin Vejnár
Added a note about non-working output stages.
Martin Vejnár
Added a sketch of Atmel's PDI interface implementation (non-working).
Martin Vejnár
Fixed output ports so that they actually work.
Martin Vejnár
Added a basic output logic controllable from nios.
Martin Vejnár
Added support for FTDI port at 115200.
Martin Vejnár
Added a missing file to sample_writer template.
Martin Vejnár
Signal pins are now tri-state by default.
Martin Vejnár
Added missing pin association (OUTH14).
Martin Vejnár
Tcl files are no longer ignored.
Martin Vejnár
Moved the components for -board directly into the project folder.
Martin Vejnár
Components for -board now have sw .tcl script.
Martin Vejnár
Added missing pll, timing specification, tcl files and fixed the SOPC frequency to 50MHz.
Martin Vejnár
merge
Martin Vejnár
Added the missing SFL files.
Martin Vejnár
Updated the TODO list.
Martin Vejnár
Added tag v1.0 for changeset ede23a287ece
Martin Vejnár
Renamed a tag.
Tags
v1.0
Martin Vejnár
merge
Martin Vejnár
Update the README with instructions on the device programming.
Martin Vejnár
Added the .cof and .cdf files.
Martin Vejnár
Removed the old firmware.
Martin Vejnár
Added the design for the Cyclone IV-based custom board.
Martin Vejnár
Added the final report for my university class.
Martin Vejnár
Added a README.
Martin Vejnár
Fixed the python client to support compression.
Martin Vejnár
Added BSP and the software for DE2 design.
Martin Vejnár
Added the missing .tcl files.
Martin Vejnár
Added a NIOS-based design for DE2 kit (as the DRAM on the cyciv board doesn't seem to work). With compression.
Martin Vejnár
Added an interval timer.
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