omicron_analyzer /

Filename Size Date modified Message
board
client
docs
firmware-board
firmware-de2
sigma_plugin
test
323 B
204 B
4.4 KB
1.1 KB

How to build

Follow these instructions to get the analyzer working on the DE2 kit. Note that I've built this using Quartus II version 10.1.

  1. Open the .qpf file in the firmware-de2 directory. Quartus II should open.
  2. Run the SOPC builder from the Tools menu.
  3. In Tools->Options, set the IP search path to firmware-de2/components folder. The builder should refresh when you click Finish. Don't do this for the -board version; the components are directly in the project folder and the SOPC builder will find them on its own.
  4. Generate the system (this may take several minutes) and exit the SOPC builder. You'll see lots of files generated in the firmware-de2 directory.
  5. Build the design in Quartus (use the Start compilation button in the toolbar).
  6. Open the Nios II IDE and import the two projects in firmware-de2/software directory.
  7. Generate the BSP (rightclick on the project, select Nios II, Generate BSP). Note that while the projects are named test and test_bsp, they are not really tests, but the final software for the design. I will rename the projects later.
  8. Copy the .h files from firmware-de2/components/* to firmware-de2/software/test_bsp/drivers/inc This step is not necessary for the -board version, there is a .tcl script that will take care of copying the driver files.
  9. Build the test project.

That's it. You can program the design into your DE2 board and upload the compiled software into it.

How to program the custom board

You'll ultimately use the JTAG pins, so open the board in Eagle and lookup the order of the pins. Note that the JTAG player should use 2.5V interface (the JTAG pins on the FPGA lack the clamp diode to VCCIO and could be damaged by the inductive overshoot). One of the pins on the JTAG header provides 2.5V for the player. I personally used the Asix Presto with its JTAG player software.

  1. Build the firmware and the software as described above, but use the sources from the firmware-board folder. The build should yield the .sof and .svf files.
  2. You won't be able to upload the design and the software separately, because you probably don't have the ByteBlaster cable and the Nios processor in the -board design doesn't have the JTAG debugger instantiated. Instead, right-click the test project in the Nios IDE and select Make targets->Build and select the only option---mem_init_install. This will generate a .hex file that you can use to initialize the on-chip ram.
  3. Now either rebuild the design or if you don't want to wait, select Processing->Update Memory Initialization File in Quartus, then rerun Assembler.
  4. The resulting .sof and .svf will now contain both the design and the software.
  5. Upload it somehow. I used Asix Presto hardware with the JTAG player software to play the .svf file into the FPGA. Remember that the design will remain configured only until the next reset.
  6. If you want to store the design permanently into the configuration memory, you can use the SFL bridge that is instantiated as a part of the design. In Quartus, select File->Convert programming file, click Open Conversion Setup Data and load the sof_to_sfljic_conversion.cof file. Then click Generate. This will create the omicron_analyzer.jic file.
  7. Open the .jic file in the Programmer (actually, the file should be open automatically as the .cdf file is part of the repository). If you display the device chain, you should see the FPGA and the configuration device.
  8. Select File->Create SVF file.
  9. Play the .svf file through JTAG interface. The design is flashed through the SFL bridge that is instantiated in the FPGA. Let me stress this again, some design with the SFL bridge must be present in the FPGA. The design that you've built in step one contains the bridge; you can simply upload the original SVF file you got after the compilation.

Note that the last step will upload the configuration into the configuration memory, but not into the FPGA itself. You need to restart the FPGA for the configuration to take effect.

How to use

Use the client/client.py script to control the analyzer. Open the script in an editor and scroll all the way down. Update the script to suit your needs and run it. The script will download the captured trace and decompress it for you.

Tip: Filter by directory path e.g. /media app.js to search for public/media/app.js.
Tip: Use camelCasing e.g. ProjME to search for ProjectModifiedEvent.java.
Tip: Filter by extension type e.g. /repo .js to search for all .js files in the /repo directory.
Tip: Separate your search with spaces e.g. /ssh pom.xml to search for src/ssh/pom.xml.
Tip: Use ↑ and ↓ arrow keys to navigate and return to view the file.
Tip: You can also navigate files with Ctrl+j (next) and Ctrl+k (previous) and view the file with Ctrl+o.
Tip: You can also navigate files with Alt+j (next) and Alt+k (previous) and view the file with Alt+o.