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pv200_avrcore / clock_div.v

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module clock_div(input RST, input CLKIN, output reg CLKOUT);

parameter top = 8'd255;
parameter width = 8;

reg[width-1:0] counter;

//assign CLKOUT = !RST && (counter == 0);

always @(posedge CLKIN or posedge RST) begin
	if (RST) begin
		counter <= top;
		CLKOUT <= 1'b0;
	end else if (counter == 0) begin
		CLKOUT <= !CLKOUT;
		counter <= top;
	end else
		counter <= counter - 1'b1;
end

endmodule