Source

vams_sim /

Filename Size Date modified Message
ex
example
1.3 KB
1.3 KB
448 B
2.3 KB
7.5 KB
1.1 KB
7.9 KB
779 B
12.0 KB
6.0 KB
835 B
11.1 KB
1.6 KB
357 B
14.7 KB
299 B

The simulator uses limecc from my yapylr project to compile the Verilog-AMS grammar to a lexer/parser. Moreover, it uses IDA solver from the sundials suite to perform the actual simulation.

Once you have the dependencies ready, you can build the package with CMake.

$ mkdir _build
$ cd _build
$ cmake ..
$ make