Source

vams_sim /

Filename Size Date modified Message
ex
example
1.3 KB
1.3 KB
448 B
1.9 KB
4.9 KB
1.1 KB
7.9 KB
767 B
10.4 KB
6.2 KB
839 B
11.2 KB
1.6 KB
357 B
14.9 KB
299 B

The simulator uses limecc from my yapylr project to compile the Verilog-AMS grammar to a lexer/parser. Moreover, it uses IDA solver from the sundials suite to perform the actual simulation.

Once you have the dependencies ready, you can build the package with CMake.

$ mkdir _build
$ cd _build
$ cmake ..
$ make