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Benoît Allard committed 4d68644

Improve convertability, and the tracebenches

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  • Parent commits e4e4b6c

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Files changed (5)

puredarwin/Core.py

 from myhdl import *
 
 import MARSparam
-from MARSparam import InstrWidth
+from MARSparam import InstrWidth, AddrWidth
 
 def RAM(raddr, dout, waddr, din, we, clk, rst_n, width, depth):
     """ Basic RAM model """
-    
+
     mem = [Signal(intbv(0)[width:]) for i in range(depth)]
 
     @always(clk.posedge)
 
     @always_comb
     def comb2():
-        if (Ofs_limit) > (limit/2):
+        if (Ofs_limit) > (limit//2):
             Ofs_fold.next = (Ofs_limit) + maxSize - limit
         else:
             Ofs_fold.next = Ofs_limit
     opcode_out = Signal(intbv(0)[5:])
     modif_out = Signal(intbv(0)[3:])
     amode_out = Signal(intbv(0)[3:])
-    anumber_out = Signal(intbv(0)[MARSparam.AddrWidth:])
+    anumber_out = Signal(intbv(0)[AddrWidth:])
     bmode_out = Signal(intbv(0)[3:])
-    bnumber_out = Signal(intbv(0)[MARSparam.AddrWidth:])
+    bnumber_out = Signal(intbv(0)[AddrWidth:])
 
     opcode_in = Signal(intbv(0)[5:])
     modif_in = Signal(intbv(0)[3:])
     amode_in = Signal(intbv(0)[3:])
-    anumber_in = Signal(intbv(0)[MARSparam.AddrWidth:])
+    anumber_in = Signal(intbv(0)[AddrWidth:])
     bmode_in = Signal(intbv(0)[3:])
-    bnumber_in = Signal(intbv(0)[MARSparam.AddrWidth:])
+    bnumber_in = Signal(intbv(0)[AddrWidth:])
 
     # Those are VHDL Aliases
     @always_comb
         amode_in.next = din[InstrWidth-8:InstrWidth-11]
         dout.next[InstrWidth-8:InstrWidth-11] = amode_out
 
-        anumber_in.next = din[InstrWidth-11:InstrWidth-11-MARSparam.AddrWidth]
-        dout.next[InstrWidth-11:InstrWidth-11-MARSparam.AddrWidth] = anumber_out
+        anumber_in.next = din[InstrWidth-11:InstrWidth-11-AddrWidth]
+        dout.next[InstrWidth-11:InstrWidth-11-AddrWidth] = anumber_out
 
-        bmode_in.next = din[MARSparam.AddrWidth+3:MARSparam.AddrWidth]
-        dout.next[MARSparam.AddrWidth+3:MARSparam.AddrWidth] = bmode_out
+        bmode_in.next = din[AddrWidth+3:AddrWidth]
+        dout.next[AddrWidth+3:AddrWidth] = bmode_out
 
-        bnumber_in.next = din[MARSparam.AddrWidth:0]
-        dout.next[MARSparam.AddrWidth:0] = bnumber_out
+        bnumber_in.next = din[AddrWidth:0]
+        dout.next[AddrWidth:0] = bnumber_out
 
         opcode_we.next = we[5]
         modif_we.next = we[4]

puredarwin/MARS.py

 from Task import TaskQueue
 from Loader import Loader
 
-InstrEmpty = Instr(t_OpCode.DAT, t_Modifier.F, t_Mode.DIRECT, Addr(), t_Mode.DIRECT, Addr())
-
 def MARS(clk, rst_n, req, ack, RX_load, draw, Winner, nbWarriors, maxTime):
-    """ MARS is the reunion of the modules """  
+    """ MARS is the reunion of the modules """
 
     t_State=enum("IDLE", "LOAD", "FETCH", "PROC")
 
     def fsm():
         if not rst_n:
             state.next = t_State.IDLE
-            ack.next = 0 
+            ack.next = 0
             Warrior.next = 0
             draw.next = True
         elif clk:
                         state.next = IDLE
                         draw.next = True
                         ack.next = True
-                        
+
     @always(state)
     def ctrl():
         if state == t_State.IDLE:
     Core_i = Core(pc=PC_i, WOfs=WOfs_i, din=WData_i, ROfs=ROfs, dout=RData_i, we=we_i, clk=clk, rst_n=rst_n, maxSize=CORESIZE)
 
     Queue_i = TaskQueue(Warrior=Warrior,IPin1=IP1_i, IPin2=IP2_i, IPout=PC_i, re=re_i, we1=we1_i, we2=we2_i, empty=empty_i, clk=clk, rst_n=rst_n, maxWarriors=nbWarriors)
-     
+
     return Proc_i, Loader_i, Core_i, Queue_i, fsm, ctrl, updateval

puredarwin/MARSparam.py

 WriteRange = 400
 
 class we:
+    WIDTH = 6
     OpCode = intbv("100000")
     Modif  = intbv("010000")
     AMod   = intbv("001000")
     I      = Full
 
 class t_OpCode:
+    # The mapping to number is free to us.\
+    ### EXCEPT for 'DAT' !
     DAT, MOV, ADD, SUB, MUL, DIV, MOD, JMP, JMZ, JMN, DJN, CMP, SNE, SLT, SPL, NOP = [intbv(i)[5:] for i in range(16)]
     SEQ = CMP
 
 class t_Modifier:
+    # The mapping into number is also free.
     A, B, AB, BA, F, X, I = [intbv(i)[3:] for i in range(7)]
 
 class t_Mode:
+    # Same here about the mapping.
     IMMEDIATE, DIRECT, A_INDIRECT, A_DECREMENT, A_INCREMENT, B_INDIRECT, B_DECREMENT, B_INCREMENT = [intbv(i)[3:] for i in range(8)]
 
 
 
 class Instr(intbv):
     def __init__(self, OpCode=None, Modifier=None, AMode=None, ANumber=None, BMode=None, BNumber=None, val=None):
-        if not val:
+        if val is None:
             val = 0
         intbv.__init__(self, val, _nrbits=InstrWidth)
-        if OpCode:
+        if OpCode is not None:
             self[InstrWidth:InstrWidth-5] = OpCode
-        if Modifier:
+        if Modifier is not None:
+            print Modifier
             self[InstrWidth-5:InstrWidth-8] = Modifier
-        if AMode:
+        if AMode is not None:
             self[InstrWidth-8:InstrWidth-11] = AMode
-        if ANumber:
+        if ANumber is not None:
             self[InstrWidth-11:InstrWidth-11-AddrWidth] = ANumber
-        if BMode:
+        if BMode is not None:
             self[AddrWidth+3:AddrWidth] = BMode
-        if BNumber:
+        if BNumber is not None:
             self[AddrWidth:] = BNumber
 
     def __getattr__(self, name):
 
     def __deepcopy__(self, visit):
         return Instr(val=self)
+
+
+InstrEmpty = Instr(t_OpCode.DAT, t_Modifier.F, t_Mode.DIRECT, Addr(), t_Mode.DIRECT, Addr())

puredarwin/Proc.py

                                              BNumber=IRA.BNumber)
                 we.next = MARSparam.we.F
             elif Modifier == t_Modifier.X:
-                WData.next = MARSparam.Instr(ANumber=IRA.Bnumber, 
+                WData.next = MARSparam.Instr(ANumber=IRA.Bnumber,
                                              BNumber=IRA.ANumber)
                 we.next = MARSparam.we.X
             elif Modifier == t_Modifier.I:
             elif Modifier == t_Modifier.BA:
                 WData.next = MARSparam.Instr(ANumber = op(OpCode, IRB.ANumber, IRA.BNumber))
                 we.next = MARSparam.we.BA
-            elif Modifier in (t_Modifier.F, 
+            elif Modifier in (t_Modifier.F,
                            t_Modifier.I):
                 WData.next = MARSparam.Instr(ANumber = op(OpCode, IRB.ANumber, IRA.ANumber),
                                              BNumber = op(OpCode, IRB.BNumber, IRA.BNumber))
                 raise ValueError(Modifier)
 
         elif OpCode == t_OpCode.DJN:
-            if Modifier in (t_Modifier.A, 
+            if Modifier in (t_Modifier.A,
                             t_Modifier.BA):
                 Num = (IRB.ANumber + MARSparam.CORESIZE - 1) % MARSparam.CORESIZE
                 WData.next = MARSparam.Instr(ANumber=Num)
     """
     We have here  three state fsm: EvalA, EvalB, The rest
     Thus we have state, thus, we need a rst(_n)
-    
+
     """
 
     t_State = enum("IDLE", "EVALOPA", "EVALOPB", "REST")
     WData_evalopa, WData_evalopb, WData_outcore = [Signal(intbv(0)[MARSparam.InstrWidth:]) for i in range(3)]
 
     we_evalopa, we_evalopb, we_outcore = [Signal(intbv(0)[6:]) for i in range(3)]
-    
+
     req_evalopa, ack_evalopa, req_evalopb, ack_evalopb = [Signal(bool()) for i in range(4)]
 
     we1_outqueue, we2_outqueue = [Signal(bool()) for i in range(2)]
                 if req:
                     state.next = t_State.EVALOPA
             elif state == t_State.EVALOPA:
-                # we could jump to REST if evalopa and evalopb 
-                # both don't write and if B is not dependant 
+                # we could jump to REST if evalopa and evalopb
+                # both don't write and if B is not dependant
                 # on A's output
                 if ack_evalopa:
                     state.next = t_State.EVALOPB
                 ack.next = True
             else:
                 raise ValueError("state value not allowed: %s" % state)
-            
+
     @always(state)
     def fsmcore():
         """
             WOfs.next = BNumber
         elif state == t_State.REST:
             WOfs.next = BPtr
-            # We are lucky here as REST is a one shoot process ... 
+            # We are lucky here as REST is a one shoot process ...
             we1.next = we1_outqueue
             we2.next = we2_outqueue
 

trace/traceProc.py

 
 from puredarwin.Proc import Proc
 
-InstrEmpty = Instr(t_OpCode.DAT, t_Modifier.F, t_Mode.DIRECT, Addr(), t_Mode.DIRECT, Addr())
-
 
 Core = {}
 Queue = []
     we1_i, we2_i, clk_i, rst_n_i, req_i, ack_i, re_i = [Signal(bool()) for i in range(7)]
     Instr_i = Signal(Instr())
     WData_i, RData_i = [Signal(intbv(InstrEmpty)) for i in range (2)]
-    we_i = Signal(intbv(0))
+    we_i = Signal(intbv(0)[MARSparam.we.WIDTH:])
 
     dut = Proc(Instr_i, PC_i, IPOut1_i, we1_i, IPOut2_i, we2_i, WOfs_i, WData_i, we_i, ROfs_i, RData_i, clk_i, rst_n_i, req_i, ack_i)