Commits

Benoît Allard  committed 95fba15

Remove the import of the puredarwin directory in runtests.py

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  • Parent commits a2df051

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Files changed (14)

File test/runtests.py

 import sys
 
 
-sys.path.append(os.path.join(
+sys.path.append(
     os.path.dirname(os.path.dirname(os.path.abspath(__file__))),
-    'puredarwin'))
+)
 
 """ Greatly imspired from Dive into Python chap. 16.7 """
 

File test/testCore.py

 
 from myhdl import Signal, intbv, Simulation, delay, traceSignals, StopSimulation
 
-from Core import Core
+from puredarwin.Core import Core
 
-import MARSparam
+from puredarwin import MARSparam
 
 class testCoreProperties(TestCase):
 

File test/testEvalOp.py

 
 from myhdl import Signal, intbv, Simulation, delay, traceSignals, StopSimulation
 
-from Proc import EvalOp
+from puredarwin.Proc import EvalOp
 
-import MARSparam
-from MARSparam import InstrWidth
+from puredarwin import MARSparam
+from puredarwin.MARSparam import InstrWidth
+
+
 class testEvalOpProperties(TestCase):
 
     def testAll(self):

File test/testFIFO.py

 
 from myhdl import Signal, intbv, Simulation, delay
 
-from Task import FIFO
+from puredarwin.Task import FIFO
 
 class TestFIFOProperties(TestCase):
 
                     yield delay(2)
                     rst_n.next = True
                     yield delay(1)
-                
+
                 self.assertEqual(empty, i in (0, 6, 7))
                 clk.next = True
                 yield delay(10) #posedge
                 self.assertEqual(empty, i == 5)
 
             re.next = False;
-           
+
         dout_i = Signal(intbv())
         din_i = Signal(intbv())
         re_i = Signal(bool(False))
 
     def testNoWriteAtOverflow(self):
         """ test that further writing has no effect when full """
-        
+
         def test(dout, din, re, we, empty, clk, rst_n):
             rst_n.next = False
             yield delay(2)
             self.assertEqual(empty, True)
             re.next = False
             we.next = False
-            
-           
+
+
         dout_i = Signal(intbv())
         din_i = Signal(intbv())
         re_i = Signal(bool(False))
 
     def testReadWhatWeWrote(self):
         """ test were we actually check that the FIFO does not manipulate data """
-        
+
         def test(dout, din, re, we, empty, clk, rst_n):
             rst_n.next = False
             yield delay(2)
                 self.assertEqual(dout, (None,11,22,33,33,44,44,55, 77, 77)[i])
             re.next = False
             we.next = False
-            
-           
+
+
         dout_i = Signal(intbv())
         din_i = Signal(intbv())
         re_i = Signal(bool(False))

File test/testFold.py

 
 from myhdl import Signal, intbv, Simulation, delay, traceSignals, StopSimulation
 
-from Core import Fold
+from puredarwin.Core import Fold
 
-import MARSparam
+from puredarwin import MARSparam
 
 class testFoldProperties(TestCase):
 

File test/testMARSparam.py

 
 import myhdl
 
-import MARSparam
+from puredarwin import MARSparam
 
 class testMARSparamProperties(unittest.TestCase):
 

File test/testOutQueue.py

 
 from myhdl import *
 
-from Proc import OutQueue
+from puredarwin.Proc import OutQueue
 
-import MARSparam
-from MARSparam import t_OpCode, t_Modifier
+from puredarwin import MARSparam
+from puredarwin.MARSparam import t_OpCode, t_Modifier
 
 class testOutQueueProperties(TestCase):
 

File test/testProc.py

 
 from myhdl import *
 
-import MARSparam
-from MARSparam import *
+from puredarwin.Proc import Proc
 
-from Proc import Proc
+from puredarwin import MARSparam
+from puredarwin.MARSparam import *
 
 InstrEmpty = Instr(t_OpCode.DAT, t_Modifier.F, t_Mode.DIRECT, Addr(), t_Mode.DIRECT, Addr())
 InstrIMP   = Instr(t_OpCode.MOV, t_Modifier.I, t_Mode.DIRECT, Addr(), t_Mode.DIRECT, Addr(1))
 
     def testIMP(self):
         """ How does the proc reacts to a basic IMP """
-        
+
         Core = {}
         if True: # IMP
             Core[CORESIZE-100] = InstrIMP
             for i in range (200):
                 clk.next = False
                 yield delay(5)
-                # set 
+                # set
                 re.next = True
                 req.next = True
 
                     # EvalOpA processed
 
                     print "Inter: %s %s %s %s %s %s %s %s" % (IPOut1, we1, IPOut2, we2, WOfs, WData, we, ROfs)
-                
+
                     clk.next = True
                     yield delay(5)
 
-                
+
                 print "Final: %s %s %s %s %s %s %s %s" % (IPOut1, we1, IPOut2, we2, WOfs, WData, we, ROfs)
-                
+
                 # check
                 self.assertEquals(IPOut1, (PC + 1) % CORESIZE)
                 self.assertEquals(we1, False)
 
             dut = Proc(Instr, PC_i, IPOut1_i, we1_i, IPOut2_i, we2_i, WOfs_i, WData_i, we_i, ROfs_i, RData_i,  clk_i, rst_n_i, req_i, ack_i)
             check = test(PC_i, re_i, IPOut1_i, we1_i, IPOut2_i, we2_i, WOfs_i, WData_i, we_i, ROfs_i, RData_i, clk_i, rst_n_i, req_i, ack_i)
-     
+
             writeC = WriteCore(we_i, WOfs_i, PC_i, WData_i, clk_i)
             readC = ReadCore(ROfs_i, PC_i, RData_i)
 

File test/testRAM.py

 from random import randrange
 from myhdl import Signal, intbv, Simulation, delay, StopSimulation
 
-from Core import RAM
+from puredarwin.Core import RAM
 
 class testRAMProperties(TestCase):
 
             yield delay(2)
             rst_n.next = True
             yield delay(1)
-            
+
             for p in range (25):
                 we.next = True
                 for i in range(10):
                     data = randrange(2**8)
                     address = randrange(128)
-                    
+
                     din.next = data
                     waddr.next = address
                     mem[address] = data
                     yield delay(3)
                     self.assertEqual(dout, mem[a])
             raise StopSimulation
-            
+
         def ClkDrv(clk):
             while True:
                 clk.next = not clk

File test/testRNG.py

 import unittest
 from unittest import TestCase
 
-from Loader import RNG
+from puredarwin.Loader import RNG
 
 class testRNG(TestCase):
 

File test/testRx.py

 
 from random import randrange
 
-from Loader import Rx, t_Parity
+from puredarwin.Loader import Rx, t_Parity
 
 import unittest
 from unittest import TestCase
                 self.assertEquals(ack, True)
                 self.assertEquals(data, totransmit)
             raise StopSimulation
-                    
+
         Rx_i, ack_i, clk_i = [Signal(bool()) for i in range(3)]
         data_i = Signal(intbv()[4:])
 
         dut = Rx(Rx=Rx_i, data=data_i, clk = clk_i, ack = ack_i, rst_n=rst_n_i, nbBits=4, baudrate=9600000, parity=t_Parity.NO, clkrate=1e9/clkPeriod)
         check = test(Rx_i, data_i, ack_i, 4)
         clock = clkDrv(clk_i)
-        
+
         sim = Simulation(dut, check, clock)
         sim.run(quiet=1)
 
                 self.assertEquals(ack, True)
                 self.assertEquals(data, totransmit)
             raise StopSimulation
-                    
+
         Rx_i, ack_i, clk_i = [Signal(bool()) for i in range(3)]
         data_i = Signal(intbv()[nbBits:])
 
         dut = Rx(Rx=Rx_i, data=data_i, clk = clk_i, ack = ack_i,rst_n = rst_n_i, nbBits=nbBits, baudrate=baudrate, parity=t_Parity.ODD, clkrate=1e9/clkPeriod)
         check = test(Rx_i, data_i, ack_i, nbBits)
         clock = clkDrv(clk_i)
-        
+
         sim = Simulation(dut, check, clock)
         sim.run(quiet=1)
 
 
 if __name__ == "__main__":
     unittest.main()
-        

File test/testSerial.py

 from myhdl import *
 
-from Loader import Rx, Tx, t_Parity
+from puredarwin.Loader import Rx, Tx, t_Parity
 
 from random import randrange
 
     """ Where we stick a Rx and a Tx together ... """
 
     def testOddParity(self):
-        
+
         nbBits = 25
         clkPeriod = 10 #ns
 
                 self.assertEquals(received, tosend)
             raise StopSimulation
 
-       
+
         Line_i = Signal(bool())
 
         clk_i, tx_req_i, tx_ack_i, rx_ack_i, rst_n_i = [Signal(bool()) for i in range(5)]
 
         data_in_i, data_out_i = [Signal(intbv()[nbBits:]) for i in range(2)]
- 
+
         txdut = Tx(Tx=Line_i, data=data_in_i, clk=clk_i, req=tx_req_i, ack=tx_ack_i, rst_n=rst_n_i, nbBits=nbBits, baudrate=baudrate, parity=t_Parity.ODD, clkrate = 1e9/clkPeriod)
         rxdut = Rx(Rx=Line_i, data=data_out_i, clk = clk_i, ack=rx_ack_i, rst_n = rst_n_i, nbBits=nbBits, baudrate=baudrate, parity=t_Parity.ODD, clkrate=1e9/clkPeriod)
         check = test(rst_n_i, data_out_i, data_in_i, tx_req_i, rx_ack_i)
 
 if __name__ == "__main__":
     unittest.main()
-        

File test/testTaskQueue.py

 
 from myhdl import Signal, intbv, Simulation, delay, traceSignals
 
-from Task import TaskQueue
+from puredarwin.Task import TaskQueue
 
 class testTaskQueueProperties(TestCase):
 

File test/testTx.py

 
 from random import randrange
 
-from Loader import Tx, t_Parity
+from puredarwin.Loader import Tx, t_Parity
 
 import unittest
 from unittest import TestCase
 
         clkPeriod = 10 # ns
         period = int (1e9 / 115200) # 115200 baud
-        
+
         def clkDrv(clk):
             while True:
                 yield delay(clkPeriod // 2)