Commits

David Schneider committed cf45d08

register allocation related fixes due to operation merges

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Files changed (2)

pypy/jit/backend/arm/assembler.py

             self.mc.gen_load_int(r.ip.value, value.getint())
             self.mc.VLDR(loc.value, r.ip.value)
 
-    # XXX needs float support
     def regalloc_mov(self, prev_loc, loc, cond=c.AL):
         if prev_loc.is_imm():
             if loc.is_reg():

pypy/jit/backend/arm/regalloc.py

         else:
             self.rm._sync_var(v)
 
-    def prepare_op_int_add(self, op, fcond):
+    def _prepare_op_int_add(self, op, fcond):
         boxes = list(op.getarglist())
         a0, a1 = boxes
         imm_a0 = _check_imm_arg(a0)
             boxes.append(box)
             l1, box = self._ensure_value_is_boxed(a1, [box])
             boxes.append(box)
+        return [l0, l1], boxes
+
+    def prepare_op_int_add(self, op, fcond):
+        locs, boxes = self._prepare_op_int_add(op, fcond)
+        self.possibly_free_vars(boxes)
         res = self.force_allocate_reg(op.result)
-        return [l0, l1, res]
+        return locs + [res]
 
-    def prepare_op_int_sub(self, op, fcond):
+    def _prepare_op_int_sub(self, op, fcond):
         boxes = list(op.getarglist())
         a0, a1 = boxes
         imm_a0 = _check_imm_arg(a0)
             boxes.append(box)
             l1, box = self._ensure_value_is_boxed(a1, boxes)
             boxes.append(box)
+        return [l0, l1], boxes
+
+    def prepare_op_int_sub(self, op, fcond):
+        locs, boxes = self._prepare_op_int_sub(op, fcond)
+        self.possibly_free_vars(boxes)
         res = self.force_allocate_reg(op.result)
-        return [l0, l1, res]
+        return locs + [res]
 
     def prepare_op_int_mul(self, op, fcond):
         boxes = list(op.getarglist())
 
 
     def prepare_guard_int_add_ovf(self, op, guard, fcond):
-        boxes = self.prepare_op_int_add(op, fcond)
-        locs = self._prepare_guard(guard, boxes)
+        locs, boxes = self._prepare_op_int_add(op, fcond)
+        res = self.force_allocate_reg(op.result)
+        locs.append(res)
+        locs = self._prepare_guard(guard, locs)
+        self.possibly_free_vars(boxes)
         self.possibly_free_vars_for_op(op)
         self.possibly_free_vars(guard.getfailargs())
         return locs
 
     def prepare_guard_int_sub_ovf(self, op, guard, fcond):
-        boxes = self.prepare_op_int_sub(op, fcond)
-        locs = self._prepare_guard(guard, boxes)
+        locs, boxes = self._prepare_op_int_sub(op, fcond)
+        res = self.force_allocate_reg(op.result)
+        locs.append(res)
+        locs = self._prepare_guard(guard, locs)
+        self.possibly_free_vars(boxes)
         self.possibly_free_vars_for_op(op)
         self.possibly_free_vars(guard.getfailargs())
         return locs