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David Schneider committed f7de9f2

add support for moving values between vfp registers and simplify the same_as operation

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  • Parent commits b083504
  • Branches arm-backed-float

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Files changed (3)

pypy/jit/backend/arm/assembler.py

             self.mc.VMOV_rc(loc.value, loc.value+1, prev_loc.value, cond=cond)
         elif loc.is_vfp_reg() and prev_loc.is_reg():
             self.mc.VMOV_cr(loc.value, prev_loc.value, prev_loc.value+1, cond=cond)
+        elif loc.is_vfp_reg() and prev_loc.is_vfp_reg():
+            self.mc.VMOV_cc(loc.value, prev_loc.value, cond=cond)
         else:
             assert 0, 'unsupported case'
     mov_loc_loc = regalloc_mov

pypy/jit/backend/arm/codebuilder.py

                 | (dm & 0xF))
         self.write32(instr)
 
+    def VMOV_cc(self, dd, dm, cond=cond.AL):
+        sz = 1 # for 64-bit mode
+        instr = (cond << 28
+                | 0xEB << 20
+                | (dd & 0xF) << 12
+                | 0x5 << 9
+                | (sz & 0x1) << 8
+                | 0x1 << 6
+                | (dm & 0xF))
+        self.write32(instr)
+
     def VCVT_float_to_int(self, target, source, cond=cond.AL):
         opc2 = 0x5
         sz = 1

pypy/jit/backend/arm/opassembler.py

 
     def emit_op_same_as(self, op, arglocs, regalloc, fcond):
         argloc, resloc = arglocs
-        if argloc.is_imm():
-            self.mc.MOV_ri(resloc.value, argloc.getint())
-        else:
-            self.mc.MOV_rr(resloc.value, argloc.value)
+        self.mov_loc_loc(argloc, resloc)
         return fcond
 
     def emit_op_guard_no_exception(self, op, arglocs, regalloc, fcond):