35#ifndef _BLAZE_MATH_SIMD_BITAND_H_
36#define _BLAZE_MATH_SIMD_BITAND_H_
68 operator&(
const SIMDi8<T>& a,
const SIMDi8<T>& b )
noexcept
69#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
71 return _mm512_and_si512( (*a).value, (*b).value );
75 return _mm256_and_si256( (*a).value, (*b).value );
79 return _mm_and_si128( (*a).value, (*b).value );
100 operator&(
const SIMDi8<T1>& a,
const SIMDi8<T2>& b )
noexcept
101#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
103 return _mm512_and_si512( (*a).value, (*b).value );
107 return _mm256_and_si256( (*a).value, (*b).value );
111 return _mm_and_si128( (*a).value, (*b).value );
129template<
typename T >
131 operator&(
const SIMDci8<T>& a,
const SIMDci8<T>& b )
noexcept
132#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
134 return _mm512_and_si512( (*a).value, (*b).value );
138 return _mm256_and_si256( (*a).value, (*b).value );
142 return _mm_and_si128( (*a).value, (*b).value );
168template<
typename T >
170 operator&(
const SIMDi16<T>& a,
const SIMDi16<T>& b )
noexcept
171#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
173 return _mm512_and_si512( (*a).value, (*b).value );
177 return _mm256_and_si256( (*a).value, (*b).value );
181 return _mm_and_si128( (*a).value, (*b).value );
202 operator&(
const SIMDi16<T1>& a,
const SIMDi16<T2>& b )
noexcept
203#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
205 return _mm512_and_si512( (*a).value, (*b).value );
209 return _mm256_and_si256( (*a).value, (*b).value );
213 return _mm_and_si128( (*a).value, (*b).value );
231template<
typename T >
233 operator&(
const SIMDci16<T>& a,
const SIMDci16<T>& b )
noexcept
234#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
236 return _mm512_and_si512( (*a).value, (*b).value );
240 return _mm256_and_si256( (*a).value, (*b).value );
244 return _mm_and_si128( (*a).value, (*b).value );
270template<
typename T >
272 operator&(
const SIMDi32<T>& a,
const SIMDi32<T>& b )
noexcept
273#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
275 return _mm512_and_si512( (*a).value, (*b).value );
279 return _mm256_and_si256( (*a).value, (*b).value );
283 return _mm_and_si128( (*a).value, (*b).value );
304 operator&(
const SIMDi32<T1>& a,
const SIMDi32<T2>& b )
noexcept
305#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
307 return _mm512_and_si512( (*a).value, (*b).value );
311 return _mm256_and_si256( (*a).value, (*b).value );
315 return _mm_and_si128( (*a).value, (*b).value );
333template<
typename T >
335 operator&(
const SIMDci32<T>& a,
const SIMDci32<T>& b )
noexcept
336#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
338 return _mm512_and_si512( (*a).value, (*b).value );
342 return _mm256_and_si256( (*a).value, (*b).value );
346 return _mm_and_si128( (*a).value, (*b).value );
372template<
typename T >
374 operator&(
const SIMDi64<T>& a,
const SIMDi64<T>& b )
noexcept
375#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
377 return _mm512_and_si512( (*a).value, (*b).value );
381 return _mm256_and_si256( (*a).value, (*b).value );
385 return _mm_and_si128( (*a).value, (*b).value );
406 operator&(
const SIMDi64<T1>& a,
const SIMDi64<T2>& b )
noexcept
407#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
409 return _mm512_and_si512( (*a).value, (*b).value );
413 return _mm256_and_si256( (*a).value, (*b).value );
417 return _mm_and_si128( (*a).value, (*b).value );
435template<
typename T >
437 operator&(
const SIMDci64<T>& a,
const SIMDci64<T>& b )
noexcept
438#if BLAZE_AVX512F_MODE || BLAZE_MIC_MODE
440 return _mm512_and_si512( (*a).value, (*b).value );
444 return _mm256_and_si256( (*a).value, (*b).value );
448 return _mm_and_si128( (*a).value, (*b).value );
Header file for the basic SIMD types.
SIMD type for 16-bit unsigned integral data values.
SIMD type for 32-bit unsigned integral data values.
SIMD type for 64-bit unsigned integral data values.
SIMD type for 8-bit unsigned integral data values.
BLAZE_ALWAYS_INLINE const T operator&(const SIMDci64< T > &a, const SIMDci64< T > &b) noexcept=delete
Bitwise AND ('&') of two vectors of 64-bit integral complex SIMD values.
#define BLAZE_ALWAYS_INLINE
Platform dependent setup of an enforced inline keyword.
Definition: Inline.h:85
System settings for the inline keywords.
System settings for the SSE mode.