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Cliff Biffle  committed 6bd3f98

Fixed some out-of-date comments in the VGA driver.

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File kernal/vga-driver.s

 @ We use a single channel of PWM (PWM1.2) to generate the horizontal sync
 @ signal without CPU intervention.  For all video modes currently under
 @ consideration, the horizontal sync rate is 31.469kHz.  We approximate this
-@ to 75MHz / 3 / 800 = 31.250kHz -- 0.6% error.  The hsync signal is negative
+@ to 100MHz / 4 / 800 = 31.250kHz -- 0.6% error.  The hsync signal is negative
 @ polarity (the sync pulse goes low).
 @
-@ We generate the pixel clock by dividing the 75MHz system clock down by 3,
+@ We generate the pixel clock by dividing the 100MHz system clock down by 4,
 @ to produce a 25MHz clock.  This is technically wrong by the same amount
 @ as hsync (a little over 0.6%), but monitors seem to do okay.  The pixels
 @ themselves are clocked out eight at a time by the I2S unit.