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Christopher Felton committed 064d62f Merge

merged

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  • Parent commits f5040ac, 540ce06

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Files changed (2)

mycores/aic23/aic23_top.v

 // File: aic23_top.v
 // Generated by MyHDL 0.8dev
-// Date: Mon Aug 27 22:14:24 2012
+// Date: Tue Aug 28 05:27:28 2012
 
 
 `timescale 1ns/10ps
 input clock_in;
 input reset_in;
 output AUDIO_CLK;
+wire AUDIO_CLK;
 input AUDIO_BCLK;
 output AUDIO_DIN;
 wire AUDIO_DIN;
 wire oclk_n;
 reg [31:0] au_in_r;
 wire oclk;
+wire dcm_locked;
 reg [31:0] cnt;
 wire _clock;
 reg [31:0] au_out_l;
 
 
 //assign _clock = 0;
-//assign clk96MHz = 0;
-//assign clk48MHz = 0;
-//assign clk12MHz = 0;
 assign g_aic23_pgm = 0;
 
 

mycores/aic23/xip.py

     def hdl_touch_inputs():
         LOCKED_OUT.next = True | CLKIN_IN | RST_IN;
 
+    CLKDV_OUT.driven = "wire"
+    CLKIN_IBUFG_OUT.driven = "wire"
+    CLK0_OUT.driven = "wire"
+    CLKFX_OUT.driven = "wire"
+    LOCKED_OUT.driven = "wire"
+
     return hdl_clkfx, hdl_clk0, hdl_clkdv, hdl_touch_inputs
 
 dcm12MHz.verilog_instance = "ICLK"
             if CE:
                 Q.next = D0 | D1 | k
 
+    
+    Q.driven = "wire"
+
     return hdl_1, hdl_2
 
 OFDDRCPE.verilog_instance = "DDR_CLK"