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Christopher Felton committed 0f0f31f

updated to the latest 0.8dev and testnig always_seq conversion

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File mycores/aic23/aic23_top.v

 // File: aic23_top.v
 // Generated by MyHDL 0.8dev
-// Date: Sun Aug 26 22:01:50 2012
+// Date: Mon Aug 27 22:07:31 2012
 
 
 `timescale 1ns/10ps

File mycores/aic23/xip.py

 
 def convert():
     clock = Signal(False)
-    reset = ResetSignal(True, active=0, async=True)
+    reset = Signal(True)
     clk12MHz = Signal(False)
     _clock = Signal(False)
     clk48MHz = Signal(False)
     clk96MHz = Signal(False)
     dcm_locked = Signal(False)
 
-    toVerilog(mydcm, clock, reset, clk12MHz, _clock, 
+    toVerilog(dcm12MHz, clock, reset, clk12MHz, _clock, 
               clk48MHz, clk96MHz, dcm_locked)
 
 if __name__ == '__main__':

File stitch/stitch_top.v

 // File: stitch_top.v
 // Generated by MyHDL 0.8dev
-// Date: Tue Jun 26 22:47:34 2012
+// Date: Mon Aug 27 21:41:26 2012
 
 
 `timescale 1ns/10ps