# Commits

committed 382f5a9

added an example the demonstrates an error in the toVHDL conversion

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• Parent commits f0e7cc0
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# File math/example_math.py

• Ignore whitespace
`+`
`+import os`
`+import time`
`+from myhdl import *`
`+`
`+def math_abcd(a,b,c,d,x):`
`+    @always_comb`
`+    def hdl():`
`+        x.next = a + b - (c + d)`
`+    return hdl`
`+`
`+def math_abcd_(a,b,c,d,x):`
`+    @always_comb`
`+    def hdl():`
`+        x.next = a + b - c - d`
`+    return hdl`
`+`
`+def example_math():`
`+    Omax = 32`
`+    a = Signal(intbv(0, min=0, max=Omax))`
`+    b = Signal(intbv(0, min=0, max=Omax))`
`+    c = Signal(intbv(0, min=0, max=Omax))`
`+    d = Signal(intbv(0, min=0, max=Omax))`
`+`
`+    Xmin,Xmax = (-1*(Omax*4), Omax*4)`
`+    x = Signal(intbv(0, min=Xmin, max=Xmax))`
`+    y = Signal(intbv(0, min=Xmin, max=Xmax))`
`+    `
`+    tb_dut1 = math_abcd(a,b,c,d,x)`
`+    tb_dut2 = math_abcd_(a,b,c,d,y)`
`+`
`+    # intended to be a convertible testbench, only convertible`
`+    # constructs can be used.`
`+    @instance`
`+    def tb_stim():`
`+        print('   start')`
`+        nxerr = 0`
`+        nyerr = 0`
`+        for aa in range(a.min, a.max):`
`+            for bb in range(b.min, b.max):`
`+                for cc in range (c.min, c.max):`
`+                    for dd in range(d.min, d.max):`
`+                        a.next = aa`
`+                        b.next = bb`
`+                        c.next = cc`
`+                        d.next = dd`
`+                        yield delay(4)`
`+                        `
`+                        xx = (aa+bb - (cc+dd))`
`+                        if not (x == xx):`
`+                            nxerr += 1`
`+                            if nxerr == 1:`
`+                                print('   x != xx, %d != %d' % (x, xx))`
`+                                print('   %d != %d+%d - (%d+%d)' % (x,a,b,c,d))`
`+                                print('   %d == %d+%d - (%d+%d)' % (xx,aa,bb,cc,dd))`
`+                            #raise StopSimulation`
`+                        #assert x == xx`
`+`
`+                        yy = (aa+bb - (cc+dd))`
`+                        if not (y == yy):`
`+                            nyerr += 1`
`+                            if nyerr == 1:`
`+                                print('   y != yy, %d != %d' % (y, yy))`
`+                                print('   %d != %d+%d - (%d+%d)' % (y,a,b,c,d))`
`+                                print('   %d == %d+%d - (%d+%d)' % (yy,aa,bb,cc,dd))`
`+                            #raise StopSimulation`
`+                        #assert y == yy`
`+                        `
`+        print('   end, x errors %d, y errors %d' % (nxerr, nyerr))`
`+        raise StopSimulation`
`+`
`+    return tb_stim, tb_dut1, tb_dut2`
`+`
`+if __name__ == '__main__':`
`+    print('MyHDL sim')`
`+    ts = time.time()`
`+    Simulation(example_math()).run()`
`+    td = time.time() - ts`
`+    print('  MyHDL sim: .... %.3f' % (td))`
`+    `
`+    print('toVHDL and sim')`
`+    toVHDL(example_math)`
`+    ts = time.time()`
`+    os.system('ghdl -a pck_myhdl_08.vhd')`
`+    os.system('ghdl -a example_math.vhd')`
`+    os.system('ghdl -e example_math')`
`+    os.system('ghdl -r example_math')`
`+    td = time.time() - ts`
`+    print('  VHDL sim: ..... %.3f' % (td))`
`+    `
`+    print('toVerilog and sim')`
`+    toVerilog(example_math)`
`+    ts = time.time()`
`+    os.system('iverilog example_math.v')`
`+    os.system('./a.out')`
`+    td = time.time() - ts`
`+    print('  Verilog sim: .. %.3f' % (td))`
`+    `
`+    `