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Christopher Felton committed 3c0fa12

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+// File: echo1.v
+// Generated by MyHDL 0.8dev
+// Date: Tue Jul 17 21:51:08 2012
+
+
+`timescale 1ns/10ps
+
+module echo1 (
+    clock,
+    reset,
+    au_fs,
+    au_in,
+    au_out
+);
+// Single channel echo
+// 
+// The following is a basic single channel echo.  An input sample
+// is combined with a delayed version of the sample.  This module is 
+// the hardware description of the audio echo.  This description will
+// be converted to Verilog/VHDL and bit-stream generated using the 
+// vendor tools.
+// 
+// The delay is constant and set by the C_BD parameter.  
+// 
+// Ports
+// ---------------------------------------------
+//   :param au_fs:  input, sample rate strobe
+//   :param au_in:  input, audio sample input
+//   :param au_out: output, audio sample output
+//    
+// Configurable Parameters:
+// ---------------------------------------------
+//    :param C_BD:    Delay buffer depth / len
+//    :param C_BW:    Delay buffer word width
+//    :param C_SR:    Sample rate
+//    :param C_SW:    Input sample bit width
+//    :param XDEVICE: Which Xilinx FPGA (BRAM utilization)
+
+input clock;
+input reset;
+input au_fs;
+input [23:0] au_in;
+output [23:0] au_out;
+reg [23:0] au_out;
+
+reg _fs;
+reg signed [23:0] _in;
+reg [13:0] rd_ptr;
+reg signed [23:0] _out;
+reg [13:0] wr_ptr;
+
+reg signed [15:0] mem [0:16384-1];
+
+
+
+
+always @(posedge clock, negedge reset) begin: ECHO1_HDL_DESC
+    if ((reset == 0)) begin
+        rd_ptr <= 0;
+        wr_ptr <= 0;
+        _fs <= 1'b0;
+        _in <= 0;
+        _out <= 0;
+        au_out <= 0;
+    end
+    else begin
+        if ((rd_ptr != wr_ptr)) begin
+            rd_ptr <= wr_ptr;
+        end
+        else begin
+            _fs <= au_fs;
+            _in <= au_in;
+            if (_fs) begin
+                mem[wr_ptr] <= $signed(_in >>> (8 + 1));
+                wr_ptr <= ((wr_ptr + 1) % 16384);
+                rd_ptr <= ((wr_ptr + 1) % 16384);
+                _out <= (mem[rd_ptr] << 8);
+            end
+            au_out <= (_in + _out);
+        end
+    end
+end
+
+endmodule
+-- File: echo1.vhd
+-- Generated by MyHDL 0.8dev
+-- Date: Tue Jul 17 21:51:15 2012
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use std.textio.all;
+
+use work.pck_myhdl_08dev.all;
+
+entity echo1 is
+    port (
+        clock: in std_logic;
+        reset: in std_logic;
+        au_fs: in std_logic;
+        au_in: in unsigned(23 downto 0);
+        au_out: out unsigned(23 downto 0)
+    );
+end entity echo1;
+-- Single channel echo
+-- 
+-- The following is a basic single channel echo.  An input sample
+-- is combined with a delayed version of the sample.  This module is 
+-- the hardware description of the audio echo.  This description will
+-- be converted to Verilog/VHDL and bit-stream generated using the 
+-- vendor tools.
+-- 
+-- The delay is constant and set by the C_BD parameter.  
+-- 
+-- Ports
+-- ---------------------------------------------
+--   :param au_fs:  input, sample rate strobe
+--   :param au_in:  input, audio sample input
+--   :param au_out: output, audio sample output
+--    
+-- Configurable Parameters:
+-- ---------------------------------------------
+--    :param C_BD:    Delay buffer depth / len
+--    :param C_BW:    Delay buffer word width
+--    :param C_SR:    Sample rate
+--    :param C_SW:    Input sample bit width
+--    :param XDEVICE: Which Xilinx FPGA (BRAM utilization)
+
+architecture MyHDL of echo1 is
+
+signal _fs: std_logic;
+signal _in: signed (23 downto 0);
+signal rd_ptr: unsigned(13 downto 0);
+signal _out: signed (23 downto 0);
+signal wr_ptr: unsigned(13 downto 0);
+type t_array_mem is array(0 to 16384-1) of signed (15 downto 0);
+signal mem: t_array_mem;
+
+begin
+
+
+
+
+ECHO1_HDL_DESC: process (clock, reset) is
+begin
+    if (reset = '0') then
+        rd_ptr <= "00000000000000";
+        wr_ptr <= "00000000000000";
+        _fs <= '0';
+        _in <= "000000000000000000000000";
+        _out <= "000000000000000000000000";
+        au_out <= "000000000000000000000000";
+    elsif rising_edge(clock) then
+        if (rd_ptr /= wr_ptr) then
+            rd_ptr <= wr_ptr;
+        else
+            _fs <= au_fs;
+            _in <= signed(au_in);
+            if to_boolean(_fs) then
+                mem(to_integer(wr_ptr)) <= resize(shift_right(_in, (8 + 1)), 16);
+                wr_ptr <= ((wr_ptr + 1) mod 16384);
+                rd_ptr <= ((wr_ptr + 1) mod 16384);
+                _out <= shift_left(resize(mem(to_integer(rd_ptr)), 24), 8);
+            end if;
+            au_out <= unsigned(_in + _out);
+        end if;
+    end if;
+end process ECHO1_HDL_DESC;
+
+end architecture MyHDL;

echo/echo1_run_tools.py

+# Copyright (c) 2011,2012 Christopher Felton
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU Lesser General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+import sys, os
+from shutil import copyfile
+from myhdl import *
+from stroby import *
+
+from tools import *
+
+def _downloadEcho(brd, bit_file):
+    """ Download bit file to a board supported by the USBP framework.
+    This has been successfully used with the SX1 and UFO400 boards.  It 
+    should be possible to use USBP to download the nexsys unmodified.  To
+    download the DE2 modificaitons would be required to the USBP framework.
+    """
+    if brd == 'sx1':
+        brd = 'sx'
+
+    print('Download bit-file, %s,  to development board %s' %(brd, cfile))
+    try:
+        import usbp
+        usb = usbp.USBP(brd)
+        usb.ConfigFpga(bit_file)
+    except:
+        print "Failed to program board"
+
+def _createSx1Fpga(ppath):
+    """Run the Xilinx tools
+    """    
+    # set up pin configuration for the FPGA
+    fpga = Fpga(path=ppath)
+    fpga.setPin('reset', 'P13')
+    fpga.setPin('clk', 'P35')
+    fpga.setPin('led[0]', 'P90')
+    fpga.setPin('led[1]', 'P91')
+    fpga.setPin('led[2]', 'P92')
+    fpga.setPin('led[3]', 'P94')
+    fpga.setPin('led[4]', 'P95')
+    fpga.setPin('led[5]', 'P96')
+    fpga.setPin('led[6]', 'P99')
+    fpga.setPin('audio_clk', 'P63')
+    fpga.setPin('audio_bclk', 'P85')
+    fpga.setPin('audio_din', 'P62')
+    fpga.setPin('audio_lrcin', 'P65')
+    fpga.setPin('audio_lrcout', 'P68')
+    fpga.setPin('audio_csn', 'P84')
+    fpga.setPin('audio_sclk', 'P78')
+    fpga.setPin('audio_sdin', 'P79')
+    fpga.setPin('audio_mode', 'P66')
+    fpga.setPin('audio_dout', 'P69')
+    fpga.setDevice('spartan3e', 'xc3s500e', 'vq100', '-5')
+    return fpga
+
+def _runTools(fpga, ppath, vfile):
+    imp = Xilinx(ppath, 'echo1')
+    imp.setFpga(fpga)
+    imp.addHdl((vfile))
+    imp.createTcl()
+    imp.run()
+
+def ConvertRunProg(brd='sx1'):
+    """Convert the design, run it through the tools (if available), and download
+    """
+
+    SupportedBoards = ['sx1']
+    if brd not in SupportedBoards:
+        print('Board must be one of the following:')
+        print('%s' % (str(SupportedBoards)))
+        return
+    else:
+        print('Converting MyHDL to Verilog for board %s' % (brd))
+    
+    clk = Signal(False)
+    au_fs = Signal(False)
+    au_in = Signal(False)
+    au_out = Signal(False)
+
+    if brd == 'sx1':
+        # Create a Verilog for the DSPtronics Signa-X1
+        toVerilog(echo1, clk, au_fs, au_in, au_out)
+        ppath = 'ise_xilinx/echo_sx1/'
+        vfile = 'sx1_echo1.v'
+        copyfile('echo1.v', ppath+vfile)
+        fpga = _createSx1Fpga(ppath)
+        _runTools(fpga, ppath, vfile)
+    
+    else:
+        print('Incorrect board %s' % (brd))
+
+
+if __name__ == '__main__':
+    ConvertRunProg(sys.argv[1])
+
+
+
+EmbeddedMemory = {
+    'xilinx' : {'XC3S500E' :       # Spartan 3E device
+                {'bpb'   : 2048*8, # bits per BRAM
+                 'total' : 20      # Total number of BRAM available
+                 },
+                'XC6S'  :          # Spartan 6 device
+                {'bpb'   : 2048*8, # bits per BRAM
+                 'total' : 32      # Total number of BRAM available
+                 }
+                },
+
+    'lattice' : {'ECP4-50'  :       # Lattice ECP4 Device
+                 {'bpb'   : 2304*8, # bits per BRAM
+                  'total' : 64      # Total number of BRAM available
+                  }
+                 },
+
+    'altera' : {'EP4CE30' :        # Altera
+                {'bpb'   : 1024*8, # bits per BRAM
+                 'total' : 72      # Total number of BRAM available
+                 },
+                },
+}
+## Constraints for the Signa-X250 and Signal-X500
+## Pin Constraints
+NET "reset"    LOC = P13  | IOSTANDARD = LVCMOS33;
+NET "clk"      LOC = P35 | IOSTANDARD=LVCMOS33 ;
+
+NET "LED[0]" LOC = P90 | IOSTANDARD = LVCMOS33;
+NET "LED[1]" LOC = P91 | IOSTANDARD = LVCMOS33;
+NET "LED[2]" LOC = P92 | IOSTANDARD = LVCMOS33;
+NET "LED[3]" LOC = P94 | IOSTANDARD = LVCMOS33;
+NET "LED[4]" LOC = P95 | IOSTANDARD = LVCMOS33;
+NET "LED[5]" LOC = P98 | IOSTANDARD = LVCMOS33;
+NET "LED[6]" LOC = P99 | IOSTANDARD = LVCMOS33;
+
+NET "AUDIO_CLK"    LOC = P63  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_BCLK"   LOC = P85  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_DIN"    LOC = P62  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_LRCIN"  LOC = P65  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_LRCOUT" LOC = P68  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_CSN"    LOC = P84  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_SCLK"   LOC = P78  | IOSTANDARD = LVCMOS33;
+NET "AUDIO_SDIN"   LOC = P79  | IOSTANDARD = LVCMOS33;
+
+NET "AUDIO_MODE"   LOC = P66  | IOSTANDARD = LVCMOS33 | PULLUP;
+NET "AUDIO_DOUT"   LOC = P69  | IOSTANDARD = LVCMOS33;
+
+NET "TP_HDR[0]" LOC = P53 | IOSTANDARD = LVCMOS33; # DIO_10
+NET "TP_HDR[1]" LOC = P54 | IOSTANDARD = LVCMOS33; # DIO_11
+NET "TP_HDR[2]" LOC = P57 | IOSTANDARD = LVCMOS33; # DIO_12
+NET "TP_HDR[3]" LOC = P58 | IOSTANDARD = LVCMOS33; # DIO_13
+NET "TP_HDR[4]" LOC = P60 | IOSTANDARD = LVCMOS33; # DIO_14
+NET "TP_HDR[5]" LOC = P61 | IOSTANDARD = LVCMOS33; # DIO_15
+NET "TP_HDR[6]" LOC = P67 | IOSTANDARD = LVCMOS33; # DIO_16
+NET "TP_HDR[7]" LOC = P70 | IOSTANDARD = LVCMOS33; # DIO_17

echo/ise/echo1/echo1.xise

+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="../../../../common/gateware/aic23/verilog/aic_spi.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="../../../../common/gateware/aic23/verilog/aic_i2s.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="../../../../common/gateware/aic23/verilog/aic23_setup.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="../../../../common/gateware/aic23/verilog/dsync.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="../../../../common/gateware/aic23/verilog/aic23.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+    </file>
+    <file xil_pn:name="../../dspt_echo1.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="../dspt_echo1.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/dcm12MHz.xaw" xil_pn:type="FILE_XAW">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="../../sx_echo.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+    </file>
+  </files>
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+  <properties>
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+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="true" xil_pn:valueState="non-default"/>
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+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|sx1_echo" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../sx_echo.v" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sx1_echo" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="sx1_echo" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="sx1_echo_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="sx1_echo_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="sx1_echo_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="sx1_echo_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="iMPACT Project File" xil_pn:value="../flash_config.ipf" xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="echo1" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-05-01T22:28:32" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="434539441C3C0314BC9463A8A7D788A0" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>

echo/ise/echo1/ipcore_dir/dcm12MHz.xaw

+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$9ax11=(`fgn#nhjlumm+Uthbli"j|p^`lewbt'lrja}bjs.g`lj7(azo$inf`1.ksgjtbWmcy##!kcl31IM|)ph}:7=:40/240>6)?;;0=95>3/3;?40 `J:3<?5>X0912>47&198=6:=;5:1?<003HXHDZGU169BVR\XGGFRSNO\C@FJJBYDDB;37L\XZ^MMH\YDDBCESHV[ESLBH43<I[]QSB@CY^AOOLHX^HF^I<l4ASUY[JHKQVNHAR]XIUAKMKAXKEA:<6O]W[]LJI_XLMXTO=??;@PT^ZIIDPUOH_QL1038EWQ]WFDGURJKR^AOO40<I[]QSB@CY^FGVZ@KAYLGC]?:;@PT^ZIIDPUMNRKWTDPMEI753HX\VRAALX]JJVRXF\Gn7L\XZ^MMH\YWEJN:96O]W[]LJI_XZLYNXRB@GHA2<>GU_SUDBAWPV@NJ@ZBA[VGDHHo4ARQLGZQN\Al0MZTPCMIAQCR^XL;::6OXZ^AOOGSA\PZN=R@@EEKW56=F_SUH@FQ@UURVPZR^XLi0MZTPFMMTP\VB02K\VR^NRUf8ER\X[PD_DYA@L59AKQN33K_MK95LLJ2;?FJL8VH^Jh5LLJ2\FP@@W@DXX55LLJ2\KPR13JF@=5>9;BNH62623JF@>U64CMI1\4>7=2IGG4>:;BNH@S?<KEAOZRLZFg9@HNBQWK_MKRGASUa8GIMC^VNBZDJJ9:AOOAPXG\^>7NBDFC:8GIMAJVCE96MCKGZ;?FJLNQ;3<45LLJD[[GSAn2IGGKVPBTDD[LHT\j1H@FHW_EKUMACb3JF@JUQBUMVJTI_>3JF@JUQ@UU78GIMNF8;0OAEFN^FJRLBBWKST>o5LLJKM[LDRNN;;7NBDIO]JFP@@W@DXXk5LLJKM[LDRNNUDYY64CMIJJZOIk2IGGD@PPDPJKAc<KEABBR]]C^VZT@753JF@CXZPPICPAZUOAO^h7NBD_GGF@GGDC01HC@CFTUGG3>EUMH^NH;5KCL]PTg=CKDUX\RGASUf8@@ULM^UJHG[\T008@CUXN[OZYH@LY^OL@@g<LEFTMCJPFY31?AJKWOXN]XKACX]NKAC23MYXIC?:;EWW]ZE^KEOTOB\]EBVJKK1<LV\J@XK7;DZWAWHFDh1MMNZ@RX]IB0=AIEYN56HM_RMVVFCd3OONHOOLK^@VB<=AAGU^BDZ\8:DLQQYT\[k0JB[[_TLJPVg<NF__S[OCUD38M0=NJ\LL46GATDPMEI763CC_XH\PIORVPZR^XLi0FDZ[ES]SO7VLk2@BXYK]_WCOQ@0<DFKOII84LNAHAAg<DFI@IIQ@UU18HJQ43DBQ;6CPV@NVA2=IM]]D^F:4NNLF5>I?3FLOH_M_Ec9SLDUBWZBBJY74PHLKEVDR[h1[ECG\GOFF@==WAG]BHYF7;QPJIQ_WM8:0\_A__QKMMVGD\@\N96^\CMI5?UUCGGO?7]]JN99SWLHDLLI87_][6:PPPZOIj2YBKHV[ESLBH3=TAGMGIn5\T@PWQUYPI@^=7^ZNTTQ26>U^[]OFS^WACIPLJJST;2^D\95[RTG;?PUBWK_MK45ZSD]AQCAT=2\BIZ?m;YCT[SCU[@EE=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB?6V\T79[`gYNl8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`:;Z294X3<S90<Q95nrvx0?aej?2|n~db`gc9uawungg*:"=h4xb1p156b%<|z==>r@Ar70>FGp90M6;4>{R65>=1=0h0:??jla78;<`2|f191=6`74;48 =4=091v_9;5868;e?74:mij:766e99P1c<??32j6<==dbc5>f1fm2Y?9768:9c9564ckh<1o:l>;R7e>=1=0h0:??jla98413?<[=?14:47a;306aef03=>555k8683>4<6sZ>=65958`8277bdi?034h:4vU5f>5<6280hw^:9:959<d<6;;nhm;478d68f2g=83:197mt$e8;<>"6n3227)<?:9`8 77=081/;k4:;c6;>5<6;3:1<v*9d;64?!c=:m1/j799;%32>72<,881>95+1281<>"6<38?7)?::7:8 40=??1/=:4;;%3;>30<,8319?5+1`816>"3<3=0(>>5a:&0<?2<,:3146*<c;71?!26201/8?4:0:&77?013->26:74$5d90>"3i3<97):l:708 1c=?k1/9<49;%70>0d<,<?1:>5+56857>"203i0(8m5579'21<f3-<26<5+76866>"0k3=o7)??:c9'5`<3j2.>i7<4$4f97>o4j3:1(;m5849'2`<0j21b??4?:%4`>=3<,?o1;o54i6194?"1k32>7)8j:6`8?l16290/:n475:&5f?1e32c<>7>5$7a9<0=#>k0<n65f6g83>!0d21?0(;l57c98m1b=83.=o76:;%4a>2d<3f8?6=4+6b8;1>"1m3=i7)?l:318 4b===10c?m50;&5g?>232e947>5$7a9<0=<g;31<7*9c;:6?>i5l3:1(;m5849'2`<0j2.:o7<<;:m1e?6=,?i14854o3`94?"1k32>76a<4;29 3e=0<1/:h48b:&2g?4432e897>5$7a9<0=<g>21<7*9c;:5?!0f2>h07b8?:18'2f<?=2.=i79m;:m44?6=,?i14854}c1f>5<5290;w)8k:4c8m0?=83.=o76:;%4f>2d<3f<<6=4+6b8;1>"1m3=i76sm2783>7<729q/:i4=3:k6=?6=,?i1485+6d84f>=h>>0;6)8l:978 3c=?k10qo<i:181>5<7s-<o6?=4i4;94?"1k32>7)8j:6`8?j00290/:n475:&5a?1e32wi?:4?:383>5}#>m09?6g:9;29 3e=0<1/:h48b:9l22<72-<h65;4$7g93g=<uz9o6=4={<6;>6d<5:o1::5+1c80b>{t;:0;6?u249806>;5>3<<7)?m:358yv13290:w0:7:618 23==01v?;50;0x91>=:=16>;4:9:p6`<72;q6854=d:?1b?3>3ty8:7>52z?7<?53349<6874}r42>5<6s4>36;>4$67922=z{=:1<7?t=2g91<=#?<0>56s|3083>4}::o0=;6*85;44?xu4i3:1=v3<7;44?!122?=0q~=i:183!122?=0q~<8:183!122?=0qp`=c;295~{i:m0;6<urn3g94?7|ug8m6=4>{|l04?6=9rwe?<4?:0y~j64=83;pqc=<:182xh4<3:1=vsa3483>4}zf:<1<7?t}o14>5<6stwvqMNL{569g56f0h>=qMNM{1CDU}zHI

echo/pck_myhdl_08dev.vhd

+-- File: pck_myhdl_08dev.vhd
+-- Generated by MyHDL 0.8dev
+-- Date: Mon May 28 14:23:51 2012
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pck_myhdl_08dev is
+
+    attribute enum_encoding: string;
+
+    function to_std_logic (arg: boolean) return std_logic;
+
+    function to_std_logic (arg: integer) return std_logic;
+
+    function to_unsigned (arg: boolean; size: natural) return unsigned;
+
+    function to_signed (arg: boolean; size: natural) return signed;
+
+    function to_integer(arg: boolean) return integer;
+
+    function to_integer(arg: std_logic) return integer;
+
+    function to_unsigned (arg: std_logic; size: natural) return unsigned;
+
+    function to_signed (arg: std_logic; size: natural) return signed;
+
+    function to_boolean (arg: std_logic) return boolean;
+
+    function to_boolean (arg: unsigned) return boolean;
+
+    function to_boolean (arg: signed) return boolean;
+
+    function to_boolean (arg: integer) return boolean;
+
+    function "-" (arg: unsigned) return signed;
+
+end pck_myhdl_08dev;
+
+
+package body pck_myhdl_08dev is
+
+    function to_std_logic (arg: boolean) return std_logic is
+    begin
+        if arg then
+            return '1';
+        else
+            return '0';
+        end if;
+    end function to_std_logic;
+
+    function to_std_logic (arg: integer) return std_logic is
+    begin
+        if arg /= 0 then
+            return '1';
+        else
+            return '0';
+        end if;
+    end function to_std_logic;
+
+
+    function to_unsigned (arg: boolean; size: natural) return unsigned is
+        variable res: unsigned(size-1 downto 0) := (others => '0');
+    begin
+        if arg then
+            res(0):= '1';
+        end if;
+        return res;
+    end function to_unsigned;
+
+    function to_signed (arg: boolean; size: natural) return signed is
+        variable res: signed(size-1 downto 0) := (others => '0');
+    begin
+        if arg then
+            res(0) := '1';
+        end if;
+        return res; 
+    end function to_signed;
+
+    function to_integer(arg: boolean) return integer is
+    begin
+        if arg then
+            return 1;
+        else
+            return 0;
+        end if;
+    end function to_integer;
+
+    function to_integer(arg: std_logic) return integer is
+    begin
+        if arg = '1' then
+            return 1;
+        else
+            return 0;
+        end if;
+    end function to_integer;
+
+    function to_unsigned (arg: std_logic; size: natural) return unsigned is
+        variable res: unsigned(size-1 downto 0) := (others => '0');
+    begin
+        res(0):= arg;
+        return res;
+    end function to_unsigned;
+
+    function to_signed (arg: std_logic; size: natural) return signed is
+        variable res: signed(size-1 downto 0) := (others => '0');
+    begin
+        res(0) := arg;
+        return res; 
+    end function to_signed;
+
+    function to_boolean (arg: std_logic) return boolean is
+    begin
+        return arg = '1';
+    end function to_boolean;
+
+    function to_boolean (arg: unsigned) return boolean is
+    begin
+        return arg /= 0;
+    end function to_boolean;
+
+    function to_boolean (arg: signed) return boolean is
+    begin
+        return arg /= 0;
+    end function to_boolean;
+
+    function to_boolean (arg: integer) return boolean is
+    begin
+        return arg /= 0;
+    end function to_boolean;
+
+    function "-" (arg: unsigned) return signed is
+    begin
+        return - signed(resize(arg, arg'length+1));
+    end function "-";
+
+end pck_myhdl_08dev;
+
+

echo/snippets/snippet_guts.py

+
+if(rd_ptr != wr_ptr) :
+    rd_ptr.next = wr_ptr
+else:
+    # Register the inputs
+    _fs.next = au_fs
+    _in.next = au_in
+    
+    if _fs:
+        # Scale the echo (buffered) samples
+        mem[wr_ptr].next = _in >> (ScaleShift + EchoShift)
+        
+        # Update pointers to delay buffer
+        wr_ptr.next = (wr_ptr + 1) % C_BD
+        rd_ptr.next = (wr_ptr + 1) % C_BD
+        
+        # Output register 1, scale back to 24 bits (shifts in hw)
+        _out.next = mem[rd_ptr] << (ScaleShift)
+            
+    # Output register 2, 
+    au_out.next = _in + (_out)
+

echo/snippets/snippet_module.py

+
+def echo1(
+    clock,                  
+    reset,
+
+    # ---- Audio Interface ----
+    au_fs,                 # sample rate strobe (data valid in)
+    au_in,                 # audio input
+    au_out,                # audio output    
+    
+    # ---- Parameters ----
+    C_BD      = 8192,      # Delay Buffer depth / len   BufferLen
+    C_BW      = 16,        # Delay Buffer word width    BufferWidth
+    C_SR      = 48000,     # Sample Rate                SampleRate
+    C_SW      = 24         # Sample width input/output  SampleWidth
+    ):
+    """Single channel echo
+
+    The following is a basic single channel echo.  An input sample
+    is combined with a delayed version of the sample.  This module is 
+    the hardware description of the audio echo.  This description will
+    be converted to Verilog/VHDL and bit-stream generated using the 
+    vendor tools.
+
+    The delay is constant and set by the C_BD parameter.  
+    
+    Ports
+    ---------------------------------------------
+      :param au_fs:  input, sample rate strobe
+      :param au_in:  input, audio sample input
+      :param au_out: output, audio sample output
+       
+    Configurable Parameters:
+    ---------------------------------------------
+       :param C_BD:    Delay buffer depth / len
+       :param C_BW:    Delay buffer word width
+       :param C_SR:    Sample rate
+       :param C_SW:    Input sample bit width
+       :param XDEVICE: Which Xilinx FPGA (BRAM utilization)
+    """
+

echo/snippets/snippet_tdd.py

+
+
+for iis in xrange(len(svi)):
+    au_in.next = int(svi[iis])
+    yield au_fs.posedge
+    svo[iis] = int(au_out)
+
+# Only checking that the expected delay is non-zero
+assert svo[plsi+BD] > 0,   '1 Echo failed svo[%d] == %d' % (plsi+BD, svo[plsi+BD])
+assert svo[plsi+BD+1] < 0, '2 Echo failed svo[%d] == %d' % (plsi+BD+1, svo[plsi+BD+1])
+        
+module tb_echo1;
+
+reg clock;
+reg reset;
+reg au_fs;
+reg [23:0] au_in;
+wire [23:0] au_out;
+
+initial begin
+    $from_myhdl(
+        clock,
+        reset,
+        au_fs,
+        au_in
+    );
+    $to_myhdl(
+        au_out
+    );
+end
+
+echo1 dut(
+    clock,
+    reset,
+    au_fs,
+    au_in,
+    au_out
+);
+
+endmodule
                 psvi = svi[:BD*4]
                 psvo = svo[:BD*4]
                 stem(arange(len(psvi)), psvi, linefmt='b', markerfmt='b'+mfmt, basefmt=' ', hold=True)
+                title('Buffer Length %s' % (BD))
                 savefig('echo1_plot_stem_%s_%s_svi_only.png'%(InputSignal, BD))
                 stem(arange(len(psvo)), psvo, linefmt='g', markerfmt='g'+mfmt, basefmt=' ', hold=True)
+                title('Buffer Length %s' % (BD))
                 savefig('echo1_plot_stem_%s_%s.png'%(InputSignal, BD))
                 close('all')
 
             mrk = '.' if InputSignal.lower() == 'pulse' else ''
             plot(svi, marker=mrk)
             plot(svo, marker=mrk)
+            xlabel('Samples')
+            title('Buffer Length %s' % (BD))
             savefig('echo1_plot_%s_%s.png'%(InputSignal, BD))
             close('all')