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Christopher Felton  committed 65a7e82

cosim example

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  • Parent commits 733e71d

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Files changed (9)

File cosim/example1/cosim_inputs_only.py

+
+import os
+import sys
+import traceback
+
+from myhdl import *
+from mysig import Clock,Reset
+
+def cosim_icarus(func, **ports):
+    fn = func.func_name
+    cmd = 'iverilog -o %s %s.v tb_%s.v'%(fn,fn,fn)
+    print(cmd)
+    os.system(cmd)
+    cmd = 'vvp -m ./myhdl.vpi %s'%(fn)
+    print(cmd)
+    return Cosimulation(cmd, **ports)
+
+def m_inputs_only(clock,reset):
+    v = Signal(modbv(0)[3:])
+    
+    @always(clock.posedge)
+    def hdl():
+        vv = 0
+        if not reset:
+            vv = v + 1
+        v.next = vv
+
+    return hdl
+
+def m_inputs_outputs(clock,reset,v):
+
+    @always(clock.posedge)
+    def hdl():
+        vv = 0
+        if not reset:
+            vv = v + 1
+        v.next = vv
+
+    return hdl    
+    
+def test(tb_dut,clock,reset):
+    tb_clk = clock.gen()
+    @instance
+    def tb_stim():
+        yield reset.pulse(10)
+        while now() < 95:
+            yield delay(10)        
+        raise StopSimulation
+
+    Simulation((tb_dut,tb_clk,tb_stim)).run()
+
+def run_test(f='i'):
+    assert f in ('i','o'), "Incorrect option, must be 'i' or 'o'"
+    msg = {'i':'inputs','o':'inputs and outputs'}
+    clock,reset = (Clock(0), Reset(0,active=0,async=True))
+    v = Signal(modbv(0)[3:])
+    print('%s'%f+'-'*48)
+    if f == 'i':
+        toVerilog(m_inputs_only,clock,reset)
+        tb_dut = cosim_icarus(m_inputs_only,clock=clock,reset=reset)
+    else:
+        toVerilog(m_inputs_outputs,clock,reset,v)
+        tb_dut = cosim_icarus(m_inputs_outputs,clock=clock,reset=reset,v=v)
+
+    try:
+        test(tb_dut,clock,reset)
+    except:
+        print('%s cosimulation failed'%(msg[f]))
+        traceback.print_exc()
+    del(tb_dut)
+    print('%s'%f+'-'*48)
+    
+if __name__ == '__main__':
+    run_test(sys.argv[1])

File cosim/example1/mysig.py

+
+import myhdl
+from myhdl import instance, delay
+
+class Clock(myhdl.SignalType):    
+    def __init__(self, val, frequency=1):
+        self._frequency = frequency
+        myhdl.SignalType.__init__(self, bool(val))
+        
+    def _get_freq(self):
+        return self._frequency
+    def _set_freq(self, f):
+        self.frequency = f
+    frequency = property(_get_freq, _get_freq)
+
+    def gen(self, hticks=2):
+        self.hticks = hticks
+        @instance
+        def _clock():
+            self.next = False
+            while True:
+                yield delay(hticks)
+                self.next = not self.val
+        return _clock
+
+class Reset(myhdl.ResetSignal):
+    def __init__(self, val, active, async):
+        myhdl.ResetSignal.__init__(self,val,active,async)
+
+    def pulse(self, delays=10):
+        if isinstance(delays,(int,long)):
+            self.next = self.active
+            yield delay(delays)
+            self.next = not self.active
+        elif isinstance(delays,tuple):
+            assert len(delays) in (1,2,3), "Incorrect number of delays"
+            self.next = not self.active if len(delays)==3 else self.active
+            for dd in delays:
+                yield delay(dd)
+                self.next = not self.val
+        else:
+            raise ValueError("%s type not supported"%(type(d)))
+        
+            
+
+

File math/conftest.py

-
-import pytest
-import simulators as simu
-
-def pytest_addoption(parser):
-    parser.addoption("--all", action="store_true",
-                     help="run all simulators")
-
-
-def pytest_generate_tests(metafunc):
-    if 'sim' in metafunc.fixturenames:
-        if metafunc.config.option.all:
-            metafunc.parameterize("sim", simu.AllSims)

File math/example_math.py

-
-import os
-import time
-from myhdl import *
-
-def math_abcd(a,b,c,d,x):
-    @always_comb
-    def hdl():
-        x.next = a + b - (c + d)
-    return hdl
-
-def math_abcd_(a,b,c,d,x):
-    @always_comb
-    def hdl():
-        x.next = a + b - c - d
-    return hdl
-
-def example_math():
-    Omax = 32
-    a = Signal(intbv(0, min=0, max=Omax))
-    b = Signal(intbv(0, min=0, max=Omax))
-    c = Signal(intbv(0, min=0, max=Omax))
-    d = Signal(intbv(0, min=0, max=Omax))
-
-    Xmin,Xmax = (-1*(Omax*4), Omax*4)
-    x = Signal(intbv(0, min=Xmin, max=Xmax))
-    y = Signal(intbv(0, min=Xmin, max=Xmax))
-    
-    tb_dut1 = math_abcd(a,b,c,d,x)
-    tb_dut2 = math_abcd_(a,b,c,d,y)
-
-    # intended to be a convertible testbench, only convertible
-    # constructs can be used.
-    @instance
-    def tb_stim():
-        print('   start')
-        nxerr = 0
-        nyerr = 0
-        for aa in range(a.min, a.max):
-            for bb in range(b.min, b.max):
-                for cc in range (c.min, c.max):
-                    for dd in range(d.min, d.max):
-                        a.next = aa
-                        b.next = bb
-                        c.next = cc
-                        d.next = dd
-                        yield delay(4)
-                        
-                        xx = (aa+bb - (cc+dd))
-                        if not (x == xx):
-                            nxerr += 1
-                            if nxerr == 1:
-                                print('   x != xx, %d != %d' % (x, xx))
-                                print('   %d != %d+%d - (%d+%d)' % (x,a,b,c,d))
-                                print('   %d == %d+%d - (%d+%d)' % (xx,aa,bb,cc,dd))
-                            #raise StopSimulation
-                        #assert x == xx
-
-                        yy = (aa+bb - (cc+dd))
-                        if not (y == yy):
-                            nyerr += 1
-                            if nyerr == 1:
-                                print('   y != yy, %d != %d' % (y, yy))
-                                print('   %d != %d+%d - (%d+%d)' % (y,a,b,c,d))
-                                print('   %d == %d+%d - (%d+%d)' % (yy,aa,bb,cc,dd))
-                            #raise StopSimulation
-                        #assert y == yy
-                        
-        print('   end, x errors %d, y errors %d' % (nxerr, nyerr))
-        raise StopSimulation
-
-    return tb_stim, tb_dut1, tb_dut2
-
-if __name__ == '__main__':
-    print('MyHDL sim')
-    ts = time.time()
-    Simulation(example_math()).run()
-    td = time.time() - ts
-    print('  MyHDL sim: .... %.3f' % (td))
-    
-    print('toVHDL and sim')
-    toVHDL(example_math)
-    ts = time.time()
-    os.system('ghdl -a pck_myhdl_08.vhd')
-    os.system('ghdl -a example_math.vhd')
-    os.system('ghdl -e example_math')
-    os.system('ghdl -r example_math')
-    td = time.time() - ts
-    print('  VHDL sim: ..... %.3f' % (td))
-    
-    print('toVerilog and sim')
-    toVerilog(example_math)
-    ts = time.time()
-    os.system('iverilog example_math.v')
-    os.system('./a.out')
-    td = time.time() - ts
-    print('  Verilog sim: .. %.3f' % (td))
-    
-    

File math/setup.cfg

-
-[pytest]
-norecursedirs = myhdl

File math/simulators.py

-
-import os
-import subprocess
-import shutil
-import myhdl as _myhdl
-
-class Simulator:
-    """
-    This class is intended to be used with "testbench" method
-    of testing converted MyHDL modules.  The "testbench" method
-    refers to a convertible testbench.  The same checks that
-    are performed in the python code is performed in V* code.
-    """
-    
-    vhdl_dir = 'vhdl/'
-    verilog_dir = 'verilog/'
-    build_dir = 'build/'
-    
-    def __init__(self):
-        self.testbench = None
-        self.hdl_path = None
-
-    def _get_tb(self):
-        return self.testbench
-
-    def _set_tb(self, tb):
-        self.testbench = tb
-
-    testbench = property(_get_tb, _set_tb)
-    
-    def convert(self):
-        pass
-
-    def compile(self):
-        pass
-
-    def run(self):
-        pass
-
-# need a better name??
-class Myhdl(Simulator):
-    def run(self):
-        assert self.testbench is not None
-        _myhdl.Simulation(self.testbench()).run()
-        
-class Ghdl(Simulator):
-
-    def convert(self):
-        assert self.testbench is not None
-        tb = self.testbench        
-        self.hdl_path = os.path.join(self.vhdl_dir, tb.func_name+'.vhd')
-        self.pck_path = 'pck_myhdl_08.vhd'
-        if not os.path.isdir(self.vhdl_dir):
-            os.mkdir(self.vhdl_dir)
-        if os.path.isfile(self.hdl_path):
-            os.remove(self.hdl_path)
-        _myhdl.toVHDL(tb)
-        shutil.move(tb.func_name+'.vhd', self.vhdl_dir)
-        
-    def compile(self):
-        assert self.testbench is not None
-        # @todo: this needs to be more modular
-        print(self.pck_path)
-        subprocess.check_call(['ghdl', '-a', '%s' % (self.pck_path)])
-        subprocess.check_call(['ghdl', '-a', '%s' % (self.hdl_path)])
-        subprocess.check_call(['ghdl', '-e', '%s' % (self.testbench.func_name)])
-
-    def run(self):
-        stext = subprocess.check_output(['ghdl', '-r',
-                                         '%s' % (self.testbench.func_name)],
-                                        stderr=subprocess.STDOUT)        
-        if 'error' in stext or 'AssertionError' in stext:
-            raise StandardError('VHDL simulation failed')
-
-
-class Icarus(Simulator):        
-
-    def convert(self):
-        assert self.testbench is not None
-        tb = self.testbench
-        self.hdl_path = os.path.join(self.verilog_dir, tb.func_name+'.v')
-        if not os.path.isdir(self.verilog_dir):
-            os.mkdir(self.verilog_dir)
-        if os.path.isfile(self.hdl_path):
-            os.remove(self.hdl_path)
-        _myhdl.toVerilog(tb)
-        shutil.move(tb.func_name+'.v', self.verilog_dir)
-
-    def compile(self):
-        self.out = self.hdl_path[:-2]
-        subprocess.check_call(['iverilog',
-                               '-o',
-                               '%s' % (self.out),
-                               '%s' % (self.hdl_path)])
-
-    def run(self):
-        stext = subprocess.check_output([self.out],
-                                        stderr=subprocess.STDOUT)
-        if 'error' in stext or 'assert' in stext:
-            raise StandardError('Verilog simulation failed')
-
-
-AllSims = [Myhdl(), Ghdl(), Icarus()]

File math/test_assign_signals.py

-
-from myhdl import *
-import simulators as simu
-
-def tb_assign_signal():
-    a,p = [Signal(bool(0)) for ii in (0,0)]
-    b,q = [Signal(intbv(0)[8:]) for ii in (0,0)]
-
-    p.assign(a)
-    q.assign(b)
-
-    @instance
-    def tb_stim():
-        a.next = 0
-        b.next = 0
-        yield delay(10)
-        for ii in range(len(b)):
-            b.next = ii
-            a.next = not a
-            yield delay(10)
-            print(int(p))
-            print(q)
-
-    return tb_stim
-
-def test_assign_signal(sim):
-    sim.testbench = tb_assign_signal
-    sim.convert()
-    sim.compile()
-    sim.run()
-    
-if __name__ == '__main__':
-    for ss in [simu.myhdl(), simu.ghdl(), simu.icarus()]:
-        try:
-            test_assign_signal(ss)
-        except:
-            pass

File math/test_bit_ops.py

-
-from myhdl import *
-import simulators as simu
-
-def mod_or(a,b,c):
-
-    @always_comb
-    def hdl():
-        c.next = a or b
-
-    return hdl
-
-def testbench_or():
-    a = Signal(bool(0))
-    b = Signal(bool(0))
-    c = Signal(bool(0))
-
-    tb_dut = mod_or(a,b,c)
-    
-    @instance
-    def tb_stim():
-        yield delay(4)
-        a.next = 0; b.next = 0
-        yield delay(4)
-        assert c == 0, "%d | %d = %d" % (a,b,c)
-
-        a.next = 0; b.next = 1        
-        yield delay(4)
-        assert c == 1, "%d | %d = %d" % (a,b,c)
-
-        a.next = 1; b.next = 0
-        yield delay(4)
-        assert c == 1, "%d | %d = %d" % (a,b,c)
-
-        a.next = 1; b.next = 1
-        yield delay(4)
-        assert c == 1, "%d | %d = %d" % (a,b,c)
-
-        raise StopSimulation
-
-    return tb_dut, tb_stim
-
-def test_or(sim):
-    sim.testbench = testbench_or
-    sim.convert()
-    sim.compile()
-    sim.run()
-        
-if __name__ == '__main__':
-    for ss in [simu.myhdl(), simu.ghdl(), simu.icarus()]:
-        test_or(ss)

File math/test_math.py

-
-import time
-import subprocess
-
-from myhdl import *
-import simulators as simu
-
-        
-
-def math_abcd(a,b,c,d,x):
-    @always_comb
-    def hdl():
-        x.next = a + b - (c + d)
-    return hdl
-
-def math_abcd_(a,b,c,d,x):
-    @always_comb
-    def hdl():
-        x.next = a + b - c - d
-    return hdl
-
-def testbench_math():
-    Omax = 8
-    a = Signal(intbv(0, min=0, max=Omax))
-    b = Signal(intbv(0, min=0, max=Omax))
-    c = Signal(intbv(0, min=0, max=Omax))
-    d = Signal(intbv(0, min=0, max=Omax))
-
-    Xmin,Xmax = (-1*(Omax*4), Omax*4)
-    x = Signal(intbv(0, min=Xmin, max=Xmax))
-    y = Signal(intbv(0, min=Xmin, max=Xmax))
-    
-    tb_dut1 = math_abcd(a,b,c,d,x)
-    tb_dut2 = math_abcd_(a,b,c,d,y)
-
-    # intended to be a convertible testbench, only convertible
-    # constructs can be used.
-    @instance
-    def tb_stim():
-        print('   start')
-        nxerr = 0
-        nyerr = 0
-        for aa in range(a.min, a.max):
-            for bb in range(b.min, b.max):
-                for cc in range (c.min, c.max):
-                    for dd in range(d.min, d.max):
-                        a.next = aa
-                        b.next = bb
-                        c.next = cc
-                        d.next = dd
-                        yield delay(4)
-                        
-                        xx = (aa+bb - (cc+dd))
-                        if not (x == xx):
-                            nxerr += 1
-                            if nxerr == 1:
-                                print('   x != xx, %d != %d' % (x, xx))
-                                print('   %d != %d+%d - (%d+%d)' % (x,a,b,c,d))
-                                print('   %d == %d+%d - (%d+%d)' % (xx,aa,bb,cc,dd))
-                            #raise StopSimulation
-                        #assert x == xx
-
-                        yy = (aa+bb - (cc+dd))
-                        if not (y == yy):
-                            nyerr += 1
-                            if nyerr == 1:
-                                print('   y != yy, %d != %d' % (y, yy))
-                                print('   %d != %d+%d - (%d+%d)' % (y,a,b,c,d))
-                                print('   %d == %d+%d - (%d+%d)' % (yy,aa,bb,cc,dd))
-                            #raise StopSimulation
-                        #assert y == yy
-                        
-        print('   end, x errors %d, y errors %d' % (nxerr, nyerr))
-        assert nxerr == 0
-        assert nyerr == 0
-        raise StopSimulation
-
-    return tb_stim, tb_dut1, tb_dut2
-
-def test_math(sim):
-    sim.testbench = testbench_math
-    sim.convert()
-    sim.compile()
-    sim.run()
-    
-    #-## always run the testbench in the myhdl simulator
-    #-## to verify goodness.
-    #-#print('MyHDL sim')
-    #-#ts = time.time()
-    #-#Simulation(testbench_math()).run()
-    #-#td = time.time() - ts
-    #-#print('  MyHDL sim: .... %.3f' % (td))
-    #-#
-    #-#print('toVHDL and sim')
-    #-#toVHDL(testbench_math)
-    #-#ts = time.time()
-    #-#subprocess.check_call('ghdl -a pck_myhdl_08.vhd')
-    #-#subprocess.check_call('ghdl -a testbench_math.vhd')
-    #-#subprocess.check_call('ghdl -e testbench_math')
-    #-#subprocess.check_call('ghdl -r testbench_math')
-    #-#td = time.time() - ts
-    #-#print('  VHDL sim: ..... %.3f' % (td))
-    #-#
-    #-#print('toVerilog and sim')
-    #-#toVerilog(testbench_math)
-    #-#ts = time.time()
-    #-#subprocess.check_call('iverilog testbench_math.v')
-    #-#subprocess.check_call('./a.out')
-    #-#td = time.time() - ts
-    #-#print('  Verilog sim: .. %.3f' % (td))
-
-
-if __name__ == '__main__':
-    for ss in [simu.myhdl(), simu.ghdl(), simu.icarus()]:
-        try:
-            test_math(ss)
-        except:
-            pass
-