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Christopher Felton committed 69a0961

fixed and error in the i2s state-machine

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Files changed (7)

mycores/aic23/aic23.py

     and transfer audio to and fro.  This module will configure the AIC23 
     """
 
+    # @todo: Read in the configuration file, from the configuration file 
+    # generate the correct register configuration.
+    if ConfigOpt is None or not isinstance(ConfigOpt, Aic23Config):
+        if not isinstance(ConfigOpt, Aic23Config):
+            print("WARNING: Invalid AIC23 config type %s, results might not be as expected" % (type(ConfigOpt)))
+        ConfigOpt = Aic23Config()
+
     i2s_tst_pts = Signal(intbv(0)[5:])
         
     # Static Signal

mycores/aic23/aic23_config.py

 
     List of configuration options:
        * sample_rate : Set the sample rate, 8,32,44.1,48,96kHz
-       * iwl : input word length.  Audio sample size in bits, 16,20,24,32
+       * input_len : input word length.  Audio sample size in bits, 16,20,24,32
        * left and right : channel settings, each left and right contains
          the following
           * mute : mute line in
         argparse.Namespace.__init__(
             self,
             sample_rate=32,  # sample rate in kHz
-            iwl=16           # input word length
+            input_len=16     # input word length
             )
         self.left = argparse.Namespace(mute=False, lock=False, volume=23,
                                        hp_lock=False, hp_zero_cross=True,
                                        hp_volume=121)
    
     def __str__(self):
-        return "TBC summary of the configuration"
+        # make a simple table k dots v where is around 38
+        # #dots = 38-len(k)-3
+        s = ''
+        for k,v in self.__dict__.items():
+            if isinstance(v, argparse.Namespace):
+                s += '   %s :\n' % (k)
+                for ek,ev in v.__dict__.items():
+                    nd = 38-len(ek)-6
+                    s += '      %s %s %s\n' % (ek, '.'*nd, ev)
+            else:
+                nd = 38-len(k)-3
+                s += '   %s %s %s\n' % (k, '.'*nd, v)
+        return s
 
     def BuildRom(self):
         """
         #                             11 = DSP format, frame sync followed by two data words
         DAF = intbv('0_0100_1110') # Master mode, 32 bit word, I2S format
         iwl_t = {16:0, 20:1, 24:2, 32:3}
-        DAF[4:2] = iwl_t[self.iwl]
+        DAF[4:2] = iwl_t[self.input_len]
 
         # Sample Rate Control
         #             D8    D7     D6    D5    D4    D3    D2    D1    D0

mycores/aic23/aic23_i2s.py

     aic23_bus,   # external I2S bus
     au_bus,      # audio bus
     tst_pts,     # testpoints
-    ConfigOpt = None
+    ConfigOpt
     ):
 
     # Constants given the bit configuration
-    MaxBitCnt = ConfigOpt.iwl + 1  # 33, 25, 17, 9
+    MaxBitCnt = ConfigOpt.input_len + 1  # 33, 25, 17, 9
     lhb,llb = (2*MaxBitCnt-1, MaxBitCnt)
     rhb,rlb = (MaxBitCnt, 0)
     # max bit index of the double long register (holds left and right)
 
         if Ts:
             au_in_l.next = shift_in[lhb:llb]  # bit 65 don't care
-            au_in_r.next = shift_in[rhb:rlb]   # bit 32 don't care
+            au_in_r.next = shift_in[rhb:rlb]  # bit 32 don't care
 
 
     mb = len(au_out_l)-1
 
     @always(clock.posedge)
     def hdl_sm():
-        if reset == True:
+        if reset == False:
             state.next = States.LEFT_CH_START
             cnt.next   = 0
             en_cnt.next = False
                 #raise ValueError('Undefined State')
 
 
-            if en_cnt and bclk_p:
-                cnt.next = cnt + 1
+            if en_cnt:
+                if bclk_p:
+                    cnt.next = cnt + 1
             else:
                 cnt.next = 0
 

mycores/aic23/aic23_setup.py

     pgm,
     aic23_bus,
     # Configuration Parameters
-    ConfigOpt=None
+    ConfigOpt
     ):
     """ Static setup / configuration for the AIC23 CODEC
 
     on the configure in ConfigOpt.  This module will drive the
     AIC23 configuration bus (
     """
-    # @todo: Read in the configuration file, from the configuration file 
-    # generate the correct register configuration.
-    if ConfigOpt is None or not isinstance(ConfigOpt, Aic23Config):
-        if not isinstance(ConfigOpt, Aic23Config):
-            print("WARNING: Invalid AIC23 config type %s, results might not be as expected" % (type(ConfigOpt)))
-        ConfigOpt = Aic23Config()
+    
     config_rom,config_addr = ConfigOpt.BuildRom()
 
     # Local aliases

mycores/aic23/aic23_top.py

     """
 
     reset = ResetSignal(True, active=0, async=True)
-    au_in_r  = Signal(intbv(0)[32:]) # audio in stream to FPGA logic right channel
-    au_in_l  = Signal(intbv(0)[32:]) # audio in stream to FPGA logic left channel 
-    au_out_r = Signal(intbv(0)[32:]) # audio out stream from FPGA logic right channel
-    au_out_l = Signal(intbv(0)[32:]) # audio out stream from FPGA logic left channel
-    mic_in   = Signal(intbv(0)[32:]) # Mic audio stream
-    hp_out   = Signal(intbv(0)[32:]) # Speaker audio stream
-    Ts       = Signal(False)         # Sample rate pulse
+    iwl = ConfigOpt.input_len
+    au_in_r  = Signal(intbv(0)[iwl:]) # audio in stream to FPGA logic right channel
+    au_in_l  = Signal(intbv(0)[iwl:]) # audio in stream to FPGA logic left channel 
+    au_out_r = Signal(intbv(0)[iwl:]) # audio out stream from FPGA logic right channel
+    au_out_l = Signal(intbv(0)[iwl:]) # audio out stream from FPGA logic left channel
+    mic_in   = Signal(intbv(0)[iwl:]) # Mic audio stream
+    hp_out   = Signal(intbv(0)[iwl:]) # Speaker audio stream
+    Ts       = Signal(False)          # Sample rate pulse
 
     # The external bus to the AIC23 CODEC
     aic23_bus = Namespace(bclk=AUDIO_BCLK, din=AUDIO_DIN, dout=AUDIO_DOUT,
     if ConfigOpt is None:
         ConfigOpt = Aic23Config()
         ConfigOpt.sample_rate = 48   # 48kHz sample rate
-        ConfigOpt.iwl = 16           # 16bit samples
+        ConfigOpt.input_len = 16     # 16bit samples
 
-    g_aic23 = aic23(clk96MHz, reset, au_bus, aic23_bus, 
-                    tst_pts, ConfigOpt)
+    g_aic23 = aic23(clock=clk96MHz, 
+                    reset=reset, 
+                    au_bus=au_bus, 
+                    aic23_bus=aic23_bus, 
+                    tst_pts=tst_pts, 
+                    ConfigOpt=ConfigOpt)
 
 
     @always(clk96MHz.posedge)

mycores/aic23/i2s_model.py

     lrcin,         # Input Left / Right select
     lrcout,        # Output Left / Right select
     bclk,          # Source data clock
-    din,           # Data serial input
-    dout,          # Data serial output
+    din,           # Data serial input  (into DAC)
+    dout,          # Data serial output (out ADC)
 
     au_in_r,       # Parallel audio data
     au_in_l,       # Parallel audio data

mycores/aic23/test_aic23.py

 def test_aic23():
     
     cfgopt = Aic23Config()
-    cfgopt.iwl = 16
+    cfgopt.input_len = 16
     cfgopt.sample_rate = 48
 
     clock           = Signal(False)
     
     tst_pts         = Signal(intbv(0)[8:])
     LEDS = Signal(intbv(0)[7:])
-    auir, auil = [Signal(modbv(0)[cfgopt.iwl:]) for ii in (0,1)]
-    auor, auol = [Signal(modbv(0)[cfgopt.iwl:]) for ii in (0,1)]
-    AuMax = (2**cfgopt.iwl)-1
+    auir, auil = [Signal(modbv(0)[cfgopt.input_len:]) for ii in (0,1)]
+    auor, auol = [Signal(modbv(0)[cfgopt.input_len:]) for ii in (0,1)]
+    AuMax = (2**cfgopt.input_len)-1
     AuMin = -1*AuMax
     new_sample = Signal(False)
 
         tb_i2s = i2s_model(AUDIO_LRCIN, AUDIO_LRCOUT, AUDIO_BCLK,
                            AUDIO_DIN, AUDIO_DOUT,
                            auir, auil, auor, auol, new_sample,
-                           BitsPerLr=cfgopt.iwl)
+                           BitsPerLr=cfgopt.input_len)
 
         tb_dut = aic23_top(clock, reset, 
                            AUDIO_CLK, AUDIO_BCLK, AUDIO_DIN, AUDIO_DOUT,