Commits

Christopher Felton committed b1ed232

fixed glitch

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Files changed (2)

mycores/aic23/aic23_i2s.py

     en_cnt = Signal(False)
     
     # State types
-    _s     = enum('LEFT_CH_START',   # Falling edge LRCOUT
+    States     = enum('LEFT_CH_START',   # Falling edge LRCOUT
                   'LEFT_CH_AUDIO',   # Get data enable counter
                   'RIGHT_CH_START',  # Rising edge LRCOUT
                   'RIGHT_CH_AUDIO',  # Right channel audio data
                   )
-    state  = Signal(_s.LEFT_CH_START)
+    state  = Signal(States.LEFT_CH_START)
 
 
     @always(clock.negedge)
     @always(clock.posedge)
     def hdl_sm():
         if reset == True:
-            state.next = _s.LEFT_CH_START
+            state.next = States.LEFT_CH_START
             cnt.next   = 0
             en_cnt.next = False
         else:
-            if state == _s.LEFT_CH_START:
+            if state == States.LEFT_CH_START:
                 if lrcin_n:
-                    state.next  = _s.LEFT_CH_AUDIO
+                    state.next  = States.LEFT_CH_AUDIO
                     en_cnt.next = True
                     
-            elif state == _s.LEFT_CH_AUDIO:
+            elif state == States.LEFT_CH_AUDIO:
                 if cnt == 33:
-                    state.next  = _s.RIGHT_CH_START
+                    state.next  = States.RIGHT_CH_START
                     en_cnt.next = False
                     
-            elif state == _s.RIGHT_CH_START:
+            elif state == States.RIGHT_CH_START:
                 if lrcin_p:
-                    state.next = _s.RIGHT_CH_AUDIO
+                    state.next = States.RIGHT_CH_AUDIO
                     en_cnt.next = True
                     
-            elif state == _s.RIGHT_CH_AUDIO:
+            elif state == States.RIGHT_CH_AUDIO:
                 if cnt == 33:
-                    state.next = _s.LEFT_CH_START
+                    state.next = States.LEFT_CH_START
                     en_cnt.next = False
             else:
-                state.next = _s.LEFT_CH_START
+                state.next = States.LEFT_CH_START
                 #raise ValueError('Undefined State')
 
 

mycores/aic23/aic23_spi.py

     sclk      = Signal(False)
 
     # State types
-    _s     = enum('IDLE', 'SHIFT', 'END')
-    state  = Signal(_s.IDLE)
+    States     = enum('IDLE', 'SHIFT', 'END')
+    state  = Signal(States.IDLE)
 
     sclk_negedge = Signal(False)
 
     @always(clk.posedge)
     def rtl_simple_sm():
         if rst == False:
-            state.next = _s.IDLE
+            state.next = States.IDLE
             busy.next  = False
         else:
-            if state == _s.IDLE:
+            if state == States.IDLE:
                 if data_go:
-                    state.next = _s.SHIFT
+                    state.next = States.SHIFT
                     busy.next  = True
                 else:
                     busy.next  = False
-            elif state == _s.SHIFT:
+            elif state == States.SHIFT:
                 if bit_cnt == 17:
-                    state.next = _s.END
-            elif state == _s.END:
-                busy.next = False
-                if not data_go: #sclk_negedge and 
-                    state.next = _s.IDLE
+                    state.next = States.END
+                    busy.next = False
+            elif state == States.END:
+                if not data_go: 
+                    state.next = States.IDLE
 
             else:
                 assert False, "Invalid State"
-                state.next = _s.IDLE
+                state.next = States.IDLE
 
     @always(clk.posedge)
     def rtl_sync_outs():