Source

examples / stitch / stitch_top.v

// File: stitch_top.v
// Generated by MyHDL 0.8dev
// Date: Mon Aug 27 21:41:26 2012


`timescale 1ns/10ps

module stitch_top (
    clock,
    reset,
    adc0_clk,
    adc0_data,
    adc0_ctrl,
    dac0_clk,
    dac0_data,
    dac0_ctrl,
    adc1_clk,
    adc1_data,
    adc1_ctrl,
    dac1_clk,
    dac1_data,
    dac1_ctrl,
    mii_txclk,
    mii_txd,
    mii_txen,
    mii_txer,
    mii_rxclk,
    mii_rxd,
    mii_rxdv,
    mii_rxer,
    mii_col,
    mii_cs
);
// 

input clock;
input reset;
input adc0_clk;
input [7:0] adc0_data;
input [3:0] adc0_ctrl;
input dac0_clk;
input [7:0] dac0_data;
input [3:0] dac0_ctrl;
input adc1_clk;
input [7:0] adc1_data;
input [3:0] adc1_ctrl;
input dac1_clk;
input [7:0] dac1_data;
input [3:0] dac1_ctrl;
input mii_txclk;
input [3:0] mii_txd;
input mii_txen;
input mii_txer;
input mii_rxclk;
input [3:0] mii_rxd;
input mii_rxdv;
input mii_rxer;
input mii_col;
input mii_cs;

wire bb_clk;
wire bb_rst;






        bb_bus_controller bb(.clk(bb_clk),
                             .rst(bb_rst));
        


assign bb_clk = clock;
assign bb_rst = reset;

endmodule
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