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examples / mycores / aic23 / test_aic23.py

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from myhdl import *
from aic23 import *



if __name__ == '__main__':
    clk             = Signal(False)
    rst             = Signal(False)
    au_in_r         = Signal(intbv(0)[32:])     
    au_in_l         = Signal(intbv(0)[32:])  
    au_out_r        = Signal(intbv(0)[32:])
    au_out_l        = Signal(intbv(0)[32:])
    mic_in          = Signal(intbv(0)[32:])      
    hp_out          = Signal(intbv(0)[32:])
    Ts              = Signal(False)
    AUDIO_BCLK      = Signal(False)
    AUDIO_DIN       = Signal(False)       
    AUDIO_DOUT      = Signal(False)      
    AUDIO_LRCIN     = Signal(False)     
    AUDIO_LRCOUT    = Signal(False)    
    AUDIO_MODE      = Signal(False)      
    AUDIO_CSN       = Signal(False)       
    AUDIO_SCLK      = Signal(False)       
    AUDIO_SDIN      = Signal(False)
    tst_pts         = Signal(intbv(0)[6:])

    toVerilog(aic23, clk, rst, au_in_r, au_in_l, au_out_r, au_out_l,
              mic_in, hp_out, Ts, AUDIO_BCLK, AUDIO_DIN, AUDIO_DOUT,
              AUDIO_LRCIN, AUDIO_LRCOUT, AUDIO_MODE, AUDIO_CSN,
              AUDIO_SCLK, AUDIO_SDIN, tst_pts)