examples / mycores / aic23 / aic23_top.v

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// File: aic23_top.v
// Generated by MyHDL 0.8dev
// Date: Tue Aug 28 05:27:28 2012


`timescale 1ns/10ps

module aic23_top (
    clock_in,
    reset_in,
    AUDIO_CLK,
    AUDIO_BCLK,
    AUDIO_DIN,
    AUDIO_DOUT,
    AUDIO_LRCIN,
    AUDIO_LRCOUT,
    AUDIO_MODE,
    AUDIO_CSN,
    AUDIO_SCLK,
    AUDIO_SDIN,
    tst_pts,
    LEDS
);
// AIC23 interface
// This module contains the logic to configure the AIC23 in a default mode
// and transfer audio to and fro.

input clock_in;
input reset_in;
output AUDIO_CLK;
wire AUDIO_CLK;
input AUDIO_BCLK;
output AUDIO_DIN;
wire AUDIO_DIN;
input AUDIO_DOUT;
input AUDIO_LRCIN;
input AUDIO_LRCOUT;
input AUDIO_MODE;
output AUDIO_CSN;
reg AUDIO_CSN;
output AUDIO_SCLK;
reg AUDIO_SCLK;
output AUDIO_SDIN;
reg AUDIO_SDIN;
output [7:0] tst_pts;
reg [7:0] tst_pts;
output [6:0] LEDS;
reg [6:0] LEDS;

reg [31:0] au_in_l;
wire Ts;
wire zero;
wire oclk_n;
reg [31:0] au_in_r;
wire oclk;
wire dcm_locked;
reg [31:0] cnt;
wire _clock;
reg [31:0] au_out_l;
reg [31:0] au_out_r;
reg reset;
wire clk96MHz;
wire clk48MHz;
reg [7:0] rbits;
wire clk12MHz;
wire g_aic23_pgm;
reg [4:0] g_aic23_i2s_tst_pts;
reg [65:0] g_aic23_g_i2s_shift_in;
reg [65:0] g_aic23_g_i2s_shift_out;
reg g_aic23_g_i2s_en_cnt;
reg g_aic23_g_i2s___lout;
reg [5:0] g_aic23_g_i2s_cnt;
wire g_aic23_g_i2s_bclk_n;
wire g_aic23_g_i2s_lrcin_n;
wire g_aic23_g_i2s_dout_p;
reg g_aic23_g_i2s___lin;
reg [1:0] g_aic23_g_i2s_state;
wire g_aic23_g_i2s_dout_n;
reg g_aic23_g_i2s___dout;
wire g_aic23_g_i2s_lrcin_p;
wire g_aic23_g_i2s_bclk_p;
reg g_aic23_g_i2s__lin;
wire g_aic23_g_i2s_lrcout_p;
reg g_aic23_g_i2s__bclk;
wire g_aic23_g_i2s_lrcout_n;
reg g_aic23_g_i2s__dout;
reg g_aic23_g_i2s___bclk;
reg g_aic23_g_i2s__lout;
reg g_aic23_g_setup_aic_c_go;
reg g_aic23_g_setup__pgm;
reg [3:0] g_aic23_g_setup_reg_cnt;
reg [2:0] g_aic23_g_setup_state;
reg g_aic23_g_setup_pgm_trans;
reg g_aic23_g_setup_pgm_rst;
reg g_aic23_g_setup_aic_c_busy;
reg [15:0] g_aic23_g_setup_aic_c;
wire g_aic23_g_setup_SPI_sclk_negedge;
reg [4:0] g_aic23_g_setup_SPI_bit_cnt;
reg g_aic23_g_setup_SPI_csn;
reg [15:0] g_aic23_g_setup_SPI_shift_out;
reg [1:0] g_aic23_g_setup_SPI_state;
reg [7:0] g_aic23_g_setup_SPI_clk_cnt;
reg g_aic23_g_setup_SPI_sclk;


assign zero = 0;
assign g_aic23_pgm = 0;



always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_HDL_TEST_POINTS
    tst_pts[5-1:0] <= g_aic23_i2s_tst_pts;
    tst_pts[5] <= AUDIO_CSN;
    tst_pts[6] <= AUDIO_SCLK;
    tst_pts[7] <= AUDIO_SDIN;
end


always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_SETUP_HDL_ROM_ADDR_VAL
    case (g_aic23_g_setup_reg_cnt)
        0: g_aic23_g_setup_aic_c[9-1:0] <= 23;
        1: g_aic23_g_setup_aic_c[9-1:0] <= 23;
        2: g_aic23_g_setup_aic_c[9-1:0] <= 0;
        3: g_aic23_g_setup_aic_c[9-1:0] <= 0;
        4: g_aic23_g_setup_aic_c[9-1:0] <= 26;
        5: g_aic23_g_setup_aic_c[9-1:0] <= 0;
        6: g_aic23_g_setup_aic_c[9-1:0] <= 2;
        7: g_aic23_g_setup_aic_c[9-1:0] <= 66;
        8: g_aic23_g_setup_aic_c[9-1:0] <= 161;
        9: g_aic23_g_setup_aic_c[9-1:0] <= 1;
        default: g_aic23_g_setup_aic_c[9-1:0] <= 0;
    endcase
    case (g_aic23_g_setup_reg_cnt)
        0: g_aic23_g_setup_aic_c[16-1:9] <= 0;
        1: g_aic23_g_setup_aic_c[16-1:9] <= 1;
        2: g_aic23_g_setup_aic_c[16-1:9] <= 2;
        3: g_aic23_g_setup_aic_c[16-1:9] <= 3;
        4: g_aic23_g_setup_aic_c[16-1:9] <= 4;
        5: g_aic23_g_setup_aic_c[16-1:9] <= 5;
        6: g_aic23_g_setup_aic_c[16-1:9] <= 6;
        7: g_aic23_g_setup_aic_c[16-1:9] <= 7;
        8: g_aic23_g_setup_aic_c[16-1:9] <= 8;
        9: g_aic23_g_setup_aic_c[16-1:9] <= 9;
        default: g_aic23_g_setup_aic_c[16-1:9] <= 15;
    endcase
end


always @(posedge clk96MHz, negedge reset) begin: AIC23_TOP_G_AIC23_G_SETUP_HDL_PGM
    if (reset == 0) begin
        g_aic23_g_setup__pgm <= 0;
        g_aic23_g_setup_pgm_trans <= 0;
    end
    else
        if (((g_aic23_pgm && (!g_aic23_g_setup__pgm)) || (!g_aic23_g_setup_pgm_rst))) begin
            g_aic23_g_setup_pgm_trans <= 1'b1;
        end
        else begin
            g_aic23_g_setup_pgm_trans <= 1'b0;
        end
        g_aic23_g_setup__pgm <= g_aic23_pgm;
    end
    
    
always @(posedge clk96MHz, negedge reset) begin: AIC23_TOP_G_AIC23_G_SETUP_HDL_SM
    if (reset == 0) begin
        g_aic23_g_setup_aic_c_go <= 0;
        g_aic23_g_setup_pgm_rst <= 0;
        g_aic23_g_setup_state <= 3'b000;
        g_aic23_g_setup_reg_cnt <= 0;
    end
    else
        case (g_aic23_g_setup_state)
            3'b000: begin
                if (g_aic23_g_setup_pgm_trans) begin
                    g_aic23_g_setup_state <= 3'b001;
                end
                g_aic23_g_setup_reg_cnt <= 0;
            end
            3'b001: begin
                if ((!g_aic23_g_setup_aic_c_busy)) begin
                    g_aic23_g_setup_state <= 3'b010;
                    g_aic23_g_setup_aic_c_go <= 1'b1;
                end
            end
            3'b010: begin
                g_aic23_g_setup_aic_c_go <= 1'b0;
                g_aic23_g_setup_state <= 3'b011;
            end
            3'b011: begin
                g_aic23_g_setup_aic_c_go <= 1'b0;
                if ((!g_aic23_g_setup_aic_c_busy)) begin
                    if ((g_aic23_g_setup_reg_cnt == 9)) begin
                        g_aic23_g_setup_state <= 3'b101;
                    end
                    else begin
                        g_aic23_g_setup_state <= 3'b100;
                    end
                end
            end
            3'b100: begin
                g_aic23_g_setup_aic_c_go <= 1'b0;
                g_aic23_g_setup_state <= 3'b001;
                g_aic23_g_setup_reg_cnt <= (g_aic23_g_setup_reg_cnt + 1);
            end
            3'b101: begin
                g_aic23_g_setup_pgm_rst <= 1'b1;
                g_aic23_g_setup_aic_c_go <= 1'b0;
                if (g_aic23_g_setup_pgm_trans) begin
                    g_aic23_g_setup_state <= 3'b000;
                end
                else begin
                    g_aic23_g_setup_state <= 3'b101;
                end
            end
            default: begin
                if (1'b0 !== 1) begin
                    $display("*** AssertionError ***");
                end
                g_aic23_g_setup_aic_c_go <= 1'b0;
                g_aic23_g_setup_state <= 3'b101;
            end
        endcase
    end
    
    
always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_SETUP_SPI_RTL_SYNC_OUTS
    if ((reset == 1'b0)) begin
        g_aic23_g_setup_SPI_csn <= 1'b1;
        g_aic23_g_setup_SPI_bit_cnt <= 0;
        g_aic23_g_setup_SPI_shift_out <= g_aic23_g_setup_aic_c;
    end
    else begin
        if ((g_aic23_g_setup_aic_c_busy && (g_aic23_g_setup_SPI_bit_cnt < (18 - 1)))) begin
            if (g_aic23_g_setup_SPI_sclk_negedge) begin
                g_aic23_g_setup_SPI_csn <= 1'b0;
                g_aic23_g_setup_SPI_bit_cnt <= (g_aic23_g_setup_SPI_bit_cnt + 1);
                if ((!g_aic23_g_setup_SPI_csn)) begin
                    g_aic23_g_setup_SPI_shift_out <= ((g_aic23_g_setup_SPI_shift_out << 1) & 65535);
                end
            end
        end
        else begin
            g_aic23_g_setup_SPI_bit_cnt <= 0;
            g_aic23_g_setup_SPI_shift_out <= g_aic23_g_setup_aic_c;
            g_aic23_g_setup_SPI_csn <= 1'b1;
        end
    end
end


always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_SETUP_SPI_RTL_SIMPLE_SM
    if ((reset == 1'b0)) begin
        g_aic23_g_setup_SPI_state <= 2'b00;
        g_aic23_g_setup_aic_c_busy <= 1'b0;
    end
    else begin
        case (g_aic23_g_setup_SPI_state)
            2'b00: begin
                if (g_aic23_g_setup_aic_c_go) begin
                    g_aic23_g_setup_SPI_state <= 2'b01;
                    g_aic23_g_setup_aic_c_busy <= 1'b1;
                end
                else begin
                    g_aic23_g_setup_aic_c_busy <= 1'b0;
                end
            end
            2'b01: begin
                if ((g_aic23_g_setup_SPI_bit_cnt == 17)) begin
                    g_aic23_g_setup_SPI_state <= 2'b10;
                end
            end
            2'b10: begin
                g_aic23_g_setup_aic_c_busy <= 1'b0;
                if ((!g_aic23_g_setup_aic_c_go)) begin
                    g_aic23_g_setup_SPI_state <= 2'b00;
                end
            end
            default: begin
                if (1'b0 !== 1) begin
                    $display("*** AssertionError ***");
                end
                g_aic23_g_setup_SPI_state <= 2'b00;
            end
        endcase
    end
end



assign g_aic23_g_setup_SPI_sclk_negedge = (g_aic23_g_setup_SPI_sclk && (!g_aic23_g_setup_SPI_clk_cnt[7]));


always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_SETUP_SPI_RTL_SLOW_CLK
    g_aic23_g_setup_SPI_clk_cnt <= ((g_aic23_g_setup_SPI_clk_cnt + 1) % 256);
    g_aic23_g_setup_SPI_sclk <= g_aic23_g_setup_SPI_clk_cnt[7];
end


always @(g_aic23_g_setup_SPI_shift_out, g_aic23_g_setup_aic_c_busy, g_aic23_g_setup_SPI_csn, g_aic23_g_setup_SPI_sclk) begin: AIC23_TOP_G_AIC23_G_SETUP_SPI_RTL_ASSIGNMENTS
    AUDIO_CSN = g_aic23_g_setup_SPI_csn;
    AUDIO_SDIN = g_aic23_g_setup_SPI_shift_out[15];
    if (((!g_aic23_g_setup_aic_c_busy) || g_aic23_g_setup_SPI_csn)) begin
        AUDIO_SCLK = 1'b1;
    end
    else begin
        AUDIO_SCLK = g_aic23_g_setup_SPI_sclk;
    end
end



assign g_aic23_g_i2s_bclk_n = (g_aic23_g_i2s__bclk && (!AUDIO_BCLK));
assign g_aic23_g_i2s_bclk_p = ((!g_aic23_g_i2s__bclk) && AUDIO_BCLK);
assign g_aic23_g_i2s_dout_n = (g_aic23_g_i2s__dout && (!AUDIO_DOUT));
assign g_aic23_g_i2s_dout_p = ((!g_aic23_g_i2s__dout) && AUDIO_DOUT);
assign g_aic23_g_i2s_lrcin_n = (g_aic23_g_i2s__lin && (!AUDIO_LRCIN));
assign g_aic23_g_i2s_lrcin_p = ((!g_aic23_g_i2s__lin) && AUDIO_LRCIN);
assign g_aic23_g_i2s_lrcout_n = (g_aic23_g_i2s__lout && (!AUDIO_LRCOUT));
assign g_aic23_g_i2s_lrcout_p = ((!g_aic23_g_i2s__lout) && AUDIO_LRCOUT);


always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_I2S_HDL_SYNCDU
    g_aic23_g_i2s__bclk <= g_aic23_g_i2s___bclk;
    g_aic23_g_i2s__dout <= g_aic23_g_i2s___dout;
    g_aic23_g_i2s__lin <= g_aic23_g_i2s___lin;
    g_aic23_g_i2s__lout <= g_aic23_g_i2s___lout;
end


always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_I2S_HDL_SM
    if ((reset == 1'b1)) begin
        g_aic23_g_i2s_state <= 2'b00;
        g_aic23_g_i2s_cnt <= 0;
        g_aic23_g_i2s_en_cnt <= 1'b0;
    end
    else begin
        case (g_aic23_g_i2s_state)
            2'b00: begin
                if (g_aic23_g_i2s_lrcin_n) begin
                    g_aic23_g_i2s_state <= 2'b01;
                    g_aic23_g_i2s_en_cnt <= 1'b1;
                end
            end
            2'b01: begin
                if ((g_aic23_g_i2s_cnt == 33)) begin
                    g_aic23_g_i2s_state <= 2'b10;
                    g_aic23_g_i2s_en_cnt <= 1'b0;
                end
            end
            2'b10: begin
                if (g_aic23_g_i2s_lrcin_p) begin
                    g_aic23_g_i2s_state <= 2'b11;
                    g_aic23_g_i2s_en_cnt <= 1'b1;
                end
            end
            2'b11: begin
                if ((g_aic23_g_i2s_cnt == 33)) begin
                    g_aic23_g_i2s_state <= 2'b00;
                    g_aic23_g_i2s_en_cnt <= 1'b0;
                end
            end
            default: begin
                g_aic23_g_i2s_state <= 2'b00;
            end
        endcase
        if ((g_aic23_g_i2s_en_cnt && g_aic23_g_i2s_bclk_p)) begin
            g_aic23_g_i2s_cnt <= (g_aic23_g_i2s_cnt + 1);
        end
        else begin
            g_aic23_g_i2s_cnt <= 0;
        end
    end
end


always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_I2S_HDL_AU_IN
    if ((g_aic23_g_i2s_bclk_p && g_aic23_g_i2s_en_cnt)) begin
        g_aic23_g_i2s_shift_in <= {g_aic23_g_i2s_shift_in[65-1:0], g_aic23_g_i2s__dout};
    end
    if (Ts) begin
        au_in_l <= g_aic23_g_i2s_shift_in[65-1:33];
        au_in_r <= g_aic23_g_i2s_shift_in[32-1:0];
    end
end


always @(negedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_I2S_HDL_SYNCDN
    g_aic23_g_i2s___bclk <= AUDIO_BCLK;
    g_aic23_g_i2s___dout <= AUDIO_DOUT;
    g_aic23_g_i2s___lin <= AUDIO_LRCIN;
    g_aic23_g_i2s___lout <= AUDIO_LRCOUT;
end


always @(AUDIO_LRCOUT, AUDIO_DIN, AUDIO_DOUT, AUDIO_LRCIN, AUDIO_BCLK) begin: AIC23_TOP_G_AIC23_G_I2S_RTL_TST_PTS
    g_aic23_i2s_tst_pts[0] = AUDIO_BCLK;
    g_aic23_i2s_tst_pts[1] = AUDIO_LRCIN;
    g_aic23_i2s_tst_pts[2] = AUDIO_LRCOUT;
    g_aic23_i2s_tst_pts[3] = AUDIO_DIN;
    g_aic23_i2s_tst_pts[4] = AUDIO_DOUT;
end



assign Ts = g_aic23_g_i2s_lrcin_n;
assign AUDIO_DIN = g_aic23_g_i2s_shift_out[65];


always @(posedge clk96MHz) begin: AIC23_TOP_G_AIC23_G_I2S_HDL_AU_OUT
    if (Ts) begin
        g_aic23_g_i2s_shift_out <= {au_out_l[31], au_out_l, au_out_r[31], au_out_r};
    end
    else if ((g_aic23_g_i2s_bclk_n && g_aic23_g_i2s_en_cnt)) begin
        g_aic23_g_i2s_shift_out <= {g_aic23_g_i2s_shift_out[65-1:0], 1'h0};
    end
end

dcm12MHz ICLK(
    .CLKIN_IN(clock_in),
    .RST_IN(zero),
    .CLKDV_OUT(clk12MHz),
    .CLKIN_IBUFG_OUT(_clock),
    .CLK0_OUT(clk48MHz),
    .CLKFX_OUT(clk96MHz),
    .LOCKED_OUT(dcm_locked)
);


always @(posedge clk96MHz) begin: AIC23_TOP_HDL_LOOPBACK
    au_out_r <= au_in_r;
    au_out_l <= au_in_l;
end


always @(posedge clk12MHz, negedge reset) begin: AIC23_TOP_HDL_CNT
    if (reset == 0) begin
        cnt <= 0;
    end
    else
        cnt <= (cnt + 1);
    end
    
    
always @(posedge clk48MHz, negedge reset) begin: AIC23_TOP_HDL_LEDS
    if (reset == 0) begin
        LEDS <= 0;
    end
    else
        LEDS <= cnt[32-1:25];
    end
    
    
always @(posedge _clock, negedge reset_in) begin: AIC23_TOP_HDL_RESET
    if ((reset_in == 0)) begin
        rbits <= 0;
        reset <= 0;
    end
    else begin
        rbits <= (((rbits << 1) | 1) & 255);
        reset <= rbits[7];
    end
end



assign oclk = clk12MHz;
assign oclk_n = (!clk12MHz);

OFDDRCPE DDR_CLK(
    .Q(AUDIO_CLK),
    .C0(oclk),
    .C1(oclk_n),
    .CE(one),
    .CLR(zero),
    .D0(one),
    .D1(zero),
    .PRE(zero)
);

endmodule
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