Source

examples / mycores / aic23 / aic23_top.py


from argparse import Namespace
from myhdl import *
from aic23 import aic23
from aic23_config import Aic23Config
from mydcm import mydcm

# Pin out for different FPGA boards with AIC23
# [Comment]-------------------------+
# [FPGA Pin]-------------------+    |
# [AIC23 Pin]--------------+   |    |
# [Port Dir]-------+       |   |    |
# [Signal Name]    |       |   |    |
#                  |       |   |    |
# DSPtronics USB FPGA board|   |    |
#------------------+-------+---+----+---------------------------
#AUDIO_CLK,        Output: 25  63   This is driven by top-level DCM->DDR flop 
#AUDIO_BCLK,       Input:  3   85   I2S Serial-bit clock
#AUDIO_DIN,        Output: 4   62   I2S data out of CODEC
#AUDIO_DOUT,       Input:  6   66   I2S data in to CODEC
#AUDIO_LRCIN,      Input:  5   65   I2S DAC-word clock signal
#AUDIO_LRCOUT,     Input:  7   68   I2S ADC-word clock signal
#AUDIO_MODE,       Output: 22  69   0 - 2 wire, 1 - SPI
#AUDIO_CSN,        Output: 21  84   Control Mode chip select
#AUDIO_SCLK,       Output: 24  78   Control port serial clock
#AUDIO_SDIN,       Output: 23  79   Control port serial data
#                  |       |   |    |
# Altera Cyclone II/III DSP board   |
#------------------+-------+---+----+---------------------------
#AUDIO_CLK,        Output: 25  AB3  This is driven by top-level DCM->DDR flop 
#AUDIO_BCLK,       Input:  3   F3   I2S Serial-bit clock
#AUDIO_DIN,        Output: 4   J21  I2S data out of CODEC
#AUDIO_DOUT,       Input:  6   B13  I2S data in to CODEC
#AUDIO_LRCIN,      Input:  5   W4   I2S DAC-word clock signal
#AUDIO_LRCOUT,     Input:  7   AB2  I2S ADC-word clock signal
#AUDIO_MODE,       Output: 22  AA2  0 - 2 wire, 1 - SPI
#AUDIO_CSN,        Output: 21  AC25 Control Mode chip select
#AUDIO_SCLK,       Output: 24  R4   Control port serial clock
#AUDIO_SDIN,       Output: 23  AD2  Control port serial data

class Container(object) : pass

def aic23_top(
    # --[System Signals]--
    clock_in,  # also known as fclk
    reset_in,  # system reset
            
    # --[ External CODEC interface to AIC23, see pinout above comments ]--
    #AUDIO_CLK,      # Output:   This is driven by top-level DCM->DDR flop 
    AUDIO_BCLK,      # Input:    I2S Serial-bit clock
    AUDIO_DIN,       # Output:   I2S data out of CODEC
    AUDIO_DOUT,      # Input:    I2S data in to CODEC
    AUDIO_LRCIN,     # Input:    I2S DAC-word clock signal
    AUDIO_LRCOUT,    # Input:    I2S ADC-word clock signal
    AUDIO_MODE,      # Output:   0 - 2 wire, 1 - SPI
    AUDIO_CSN,       # Output:   Control Mode chip select
    AUDIO_SCLK,      # Output:   Control port serial clock
    AUDIO_SDIN,      # Output:   Control port serial data
    tst_pts,         # Output:   test points
    LEDS,            # Input:    7 leds
    # --[ Parameters ]--
    ConfigOpt = None
    ):
    """AIC23 interface
    This module contains the logic to configure the AIC23 in a default mode
    and transfer audio to and fro.
    """

    reset = ResetSignal(True, active=0, async=True)
    au_in_r  = Signal(intbv(0)[32:]) # audio in stream to FPGA logic right channel
    au_in_l  = Signal(intbv(0)[32:]) # audio in stream to FPGA logic left channel 
    au_out_r = Signal(intbv(0)[32:]) # audio out stream from FPGA logic right channel
    au_out_l = Signal(intbv(0)[32:]) # audio out stream from FPGA logic left channel
    mic_in   = Signal(intbv(0)[32:]) # Mic audio stream
    hp_out   = Signal(intbv(0)[32:]) # Speaker audio stream
    Ts       = Signal(False)         # Sample rate pulse
    aic23_bus = Namespace(bclk=AUDIO_BCLK, din=AUDIO_DIN, dout=AUDIO_DOUT,
                          lrcin=AUDIO_LRCIN, lrcout=AUDIO_LRCOUT, mode=AUDIO_MODE,
                          csn=AUDIO_CSN, sclk=AUDIO_SCLK, sdin=AUDIO_SDIN)
    au_bus = Namespace(in_r=au_in_r, in_l=au_in_l, out_r=au_out_r, out_l=au_out_l,
                       mic_in=mic_in, hp_out=hp_out, Ts=Ts)    
    clk12MHz = Signal(False); 
    clk48MHz = Signal(False); 
    clk96MHz = Signal(False)
    dcm_locked = Signal(False)
    _clock = Signal(False)
    g_dcm = mydcm(CLKIN_IN=clock_in, RST_IN=Signal(False), CLKDV_OUT=clk12MHz,
                  CLKIN_IBUFG_OUT=_clock, CLK0_OUT=clk48MHz,
                  CLKFX_OUT=clk96MHz, LOCKED_OUT=dcm_locked)

    rbits = Signal(intbv(0)[8:])
    @always(_clock.posedge, reset_in.negedge)
    def hdl_reset():
        if reset_in == False:
            rbits.next = 0
            reset.next = 0
        else:
            rbits.next = (rbits << 1) | 1
            reset.next = rbits[7]

    g_aic23 = aic23(clk96MHz, reset, au_bus, aic23_bus, tst_pts, ConfigOpt)


    @always(clk96MHz.posedge)
    def hdl_loopback():
        au_out_r.next = au_in_r
        au_out_l.next = au_in_l

    cnt = Signal(modbv(0)[32:])
    @always_seq(clk12MHz.posedge, reset=reset)
    def hdl_cnt():
        cnt.next = cnt+1

    @always_seq(clk48MHz.posedge, reset=reset)
    def hdl_leds():
        LEDS.next = cnt[32:25]

    return g_aic23, g_dcm, hdl_loopback, hdl_cnt, hdl_leds


def _convert(ConfigOpt):
    clock        = Signal(False)
    reset        = ResetSignal(False, active=0, async=True)
    AUDIO_BCLK   = Signal(False)
    AUDIO_DIN    = Signal(False)       
    AUDIO_DOUT   = Signal(False)      
    AUDIO_LRCIN  = Signal(False)     
    AUDIO_LRCOUT = Signal(False)    
    AUDIO_MODE   = Signal(False)      
    AUDIO_CSN    = Signal(False)       
    AUDIO_SCLK   = Signal(False)       
    AUDIO_SDIN   = Signal(False)
    tst_pts      = Signal(intbv(0)[8:])
    LEDS         = Signal(intbv(0)[7:])

    toVerilog(aic23_top, clock, reset, AUDIO_BCLK, AUDIO_DIN, AUDIO_DOUT,
              AUDIO_LRCIN, AUDIO_LRCOUT, AUDIO_MODE, AUDIO_CSN,
              AUDIO_SCLK, AUDIO_SDIN, tst_pts, LEDS)

    toVHDL(aic23_top, clock, reset, AUDIO_BCLK, AUDIO_DIN, AUDIO_DOUT,
           AUDIO_LRCIN, AUDIO_LRCOUT, AUDIO_MODE, AUDIO_CSN,
           AUDIO_SCLK, AUDIO_SDIN, tst_pts, LEDS)


def _create_parser():
    parser = None
    return parser

if __name__ == '__main__':
    _convert(Aic23Config(_create_parser()))