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Christopher Felton committed 8ad0627

updated readmes and testing

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2014/examples/README.md

 
 ## Get MyHDL 0.9dev and Build VPI
 
-   >> hg clone http://bitbucket.org/jandecaluwe/myhdl
-   >> cd myhdl
-   >> hg up -C 0.9-dev
-   >> cd cosimulation
-   >> cd icarus
-   >> make
+    >> hg clone http://bitbucket.org/jandecaluwe/myhdl
+    >> cd myhdl
+    >> hg up -C 0.9-dev
+    >> cd cosimulation
+    >> cd icarus
+    >> make
 
 ## Test VPI and Cosimulation
 
-   >> cd <to some other directory>
-   >> git clone https://github.com/cfelton/alt.hdl.git
-   >> cd alt.hdl/examples/ex6_vgasys/test_verilogs/
-   >> cp <myhdl dir>/cosimulation/icarus/myhdl.vpi .
-   # create vcd directory in ex6_vgasys/test_verilogs if needed
-   >> pwd
-   ~/alt.hdl/examples/ex6_vgasys/test_verilogs
-   >> mkdir vcd
-   >> python test_vgasys.py
+    >> cd <to some other directory>
+    >> git clone https://github.com/cfelton/alt.hdl.git
+    >> cd alt.hdl/examples/ex6_vgasys/test_verilogs/
+    >> cp <myhdl dir>/cosimulation/icarus/myhdl.vpi .
+    # create vcd directory in ex6_vgasys/test_verilogs if needed
+    >> pwd
+    ~/alt.hdl/examples/ex6_vgasys/test_verilogs
+    >> mkdir vcd
+    >> python test_vgasys.py
 
 This will take a little bit to simulate.  It should display to the 
 screan, create a VCD file in the vcd directory and eventually create
 (gsoc/2014/examples) make sure the myhdl.vpi is copy to this 
 directory and run the "test_cosim.py":
 
-   >> python test_cosim.py
+    >> python test_cosim.py
 
 This will use the models from *simmodels.py* and drive a 
 simple Verilog file.  This cosim environment is missing 
 the verification porition, that is checking the output due
 to the stimulus (input) is valid ... that will be left as
-an exercise for the student.
+an exercise for the student.

2014/examples/simple_gemac_core/README.md

 [here]()
 
 The modificaitons in this directory are the removal of the Xilinx
-specific FIFOs and the addition of a Ptyhon verification testbench.
-
+specific FIFOs and the addition of a Python verification testbench.
 
 The code in the *simple_gemac* has minimal changes, the main change
 is the fifo module names, they are slightly different.  This allows

2014/examples/simple_gemac_core/alt_fifo/m_delay_line_w10.v

 // File: m_delay_line_w10.v
 // Generated by MyHDL 0.9dev
-// Date: Tue Jul 15 22:08:27 2014
+// Date: Mon Jul 21 18:53:12 2014
 
 
 `timescale 1ns/10ps

2014/examples/simple_gemac_core/alt_fifo/m_fifo_2clock_cascade.py

 ):
 
 
-    wr = Signal(bool(0))
-    rd = Signal(bool(0))
-    rdi = Signal(bool(0))
-    wri = Signal(bool(0))
+    wr = Signal(bool(0))    # wr1
+    #wr2 = Signal(bool(0))  # rd1
+    wr3 = Signal(bool(0))
+    rd1 = Signal(bool(0))
+    rd2 = Signal(bool(0))
+    rd = Signal(bool(0))    # rd3
     ed1 = Signal(bool(1))
 
     args = Namespace(width=36, size=128, name='fifo_2clock_cascade')
     fbus2 = FIFOBus(args=args)
     args.size = 16
+    fbus1 = FIFOBus(args=args)
     fbus3 = FIFOBus(args=args)
 
     # need to update the fbus refernces to reference the Signals in
     # the moudule port list (function arguments).
-    fbus2.wr = wr
-    fbus2.wdata = datain
-    fbus2.rd = rdi
-    #fbus2.rdata =     #dataout_d
+    fbus1.wr = wr
+    fbus1.wdata = datain
+    fbus1.rd = rd1
 
-    fbus3.wr = wri
+    fbus2.wr = rd1
+    fbus2.wdata = fbus1.rdata
+    fbus2.rd = rd2
+
+    fbus3.wr = wr3
     fbus3.wdata = fbus2.rdata
     fbus3.rd = rd
     fbus3.rdata = dataout
     def rtl_assign1():
         wr.next = src_rdy_i and dst_rdy_o
         rd.next = dst_rdy_i and src_rdy_o
-        rdi.next = not ed1 and not fbus3.full
-        wri.next = fbus2.rvld
+        rd1.next = not fbus1.empty and not fbus2.full
+        rd2.next = not ed1 and not fbus3.full
+        wr3.next = fbus2.rvld
 
     @always_comb
     def rtl_assign2():
-        dst_rdy_o.next = not fbus2.full
+        dst_rdy_o.next = not fbus1.full
         src_rdy_o.next = not fbus3.empty
 
     # @todo: fix the m_fifo_async bug!!!
     # the two small FIFOs were used to simplify the interface to
     # the async FIFO, the async FIFOs have some odd behaviors, the
     # up front fast fifo wasn't really needed.
-    gfifo2 = m_fifo_async(reset, wclk, rclk, fbus2)
-
     # the small fast FIFOs have a simpler (reactive) interface
     # it works more like a register with enable(s).
+
+    gfifo1 = m_fifo_fast(wclk, reset, fbus1)
+    gfifo2 = m_fifo_async(reset, wclk, rclk, fbus2)
     gfifo3 = m_fifo_fast(rclk, reset, fbus3)
                 
 
-    return rtl_assign1, rtl_assign2, rtl_ed1, gfifo2, gfifo3
+    return rtl_assign1, rtl_assign2, rtl_ed1, gfifo1, gfifo2, gfifo3
 

2014/examples/simple_gemac_core/alt_fifo/m_fifo_2clock_cascade.v

 // File: m_fifo_2clock_cascade.v
 // Generated by MyHDL 0.9dev
-// Date: Tue Jul 15 22:08:27 2014
+// Date: Mon Jul 21 18:53:12 2014
 
 
 `timescale 1ns/10ps
 input reset;
 
 reg fbus3_empty;
-wire rdi;
+reg fbus3_full;
+reg fbus1_full;
+wire fbus2_empty;
+wire rd;
+wire fbus2_full;
+reg fbus1_empty;
 reg ed1;
-wire fbus2_empty;
-wire fbus2_rvld;
-wire wri;
-wire rd;
-reg fbus3_full;
-wire fbus2_full;
+wire rd1;
+wire rd2;
+reg fbus2_rvld;
+wire wr3;
 wire wr;
 reg [4:0] gfifo3_nvacant;
 reg [3:0] gfifo3_addr;
 reg [4:0] gfifo3_ntenant;
 wire [35:0] gfifo3_fbus_wdata;
 wire gfifo3_fbus_clear;
-wire gfifo2_rrst_n;
-reg gfifo2_p_aempty_n;
-reg gfifo2_high;
-wire [6:0] gfifo2_rgnext;
-reg [6:0] gfifo2_wbin;
 reg gfifo2_wfull;
-wire gfifo2_wrl;
-wire gfifo2_wrm;
-reg gfifo2__rvld1;
-reg gfifo2_dirset_n;
-reg [6:0] gfifo2_rbin;
-wire gfifo2_wrst_n;
-reg gfifo2_direction;
-reg gfifo2_afull_n;
-reg gfifo2_rempty2;
-reg [6:0] gfifo2_rbnext;
-reg [6:0] gfifo2_wptr;
-reg gfifo2_wfull2;
-reg [6:0] gfifo2_rptr;
-reg gfifo2_dirclr_n;
+wire [6:0] gfifo2_raddr;
+wire [6:0] gfifo2_waddr;
+reg [7:0] gfifo2_rq2_wptr;
+reg [7:0] gfifo2_wq2_rptr;
+reg [7:0] gfifo2_wptr;
+reg gfifo2_rrst;
 reg gfifo2_rempty;
-reg gfifo2__rempty;
-reg gfifo2_aempty_n;
-reg [6:0] gfifo2_wbnext;
-wire [6:0] gfifo2_wgnext;
+reg gfifo2_wrst;
+wire gfifo2__we;
+reg [7:0] gfifo2_rptr;
+reg [7:0] gfifo2_rbin;
+reg [7:0] gfifo2_wbin;
+wire [35:0] gfifo2_g_fifomem_din;
 reg [35:0] gfifo2_g_fifomem__din;
 reg [6:0] gfifo2_g_fifomem__addr_w;
 reg [35:0] gfifo2_g_fifomem__dout;
 reg gfifo2_g_fifomem__wr;
+reg [7:0] gfifo2_gs4_d1;
+reg [7:0] gfifo2_gs3_d1;
+reg [4:0] gfifo1_nvacant;
+reg [3:0] gfifo1_addr;
+wire gfifo1_fbus_rvld;
+reg [4:0] gfifo1_ntenant;
+wire gfifo1_fbus_clear;
 
 reg [35:0] gfifo3_mem [0:16-1];
-reg gfifo2_rrst_s [0:2-1];
-reg gfifo2_wrst_s [0:2-1];
 reg [35:0] gfifo2_g_fifomem_mem [0:128-1];
+reg gfifo2_gs2_rsync [0:2-1];
+reg gfifo2_gs1_rsync [0:2-1];
+reg [35:0] gfifo1_mem [0:16-1];
 
 assign gfifo3_fbus_clear = 0;
+assign gfifo1_fbus_clear = 0;
 
 
 
 
 assign wr = (src_rdy_i && dst_rdy_o);
 assign rd = (dst_rdy_i && src_rdy_o);
-assign rdi = ((!ed1) && (!fbus3_full));
-assign wri = fbus2_rvld;
+assign rd1 = ((!fbus1_empty) && (!fbus2_full));
+assign rd2 = ((!ed1) && (!fbus3_full));
+assign wr3 = fbus2_rvld;
 
 
 
-assign dst_rdy_o = (!fbus2_full);
+assign dst_rdy_o = (!fbus1_full);
 assign src_rdy_o = (!fbus3_empty);
 
 
 end
 
 
-always @(posedge rclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_RD_VLD
-    gfifo2__rvld1 <= rdi;
-    gfifo2__rempty <= gfifo2_rempty;
-end
-
-
-always @(posedge wclk, negedge gfifo2_dirset_n, negedge gfifo2_dirclr_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_ASYNC_CMP
-    if ((!gfifo2_dirclr_n)) begin
-        gfifo2_direction <= 1'b0;
-    end
-    else if ((!gfifo2_dirset_n)) begin
-        gfifo2_direction <= 1'b1;
-    end
-    else begin
-        if ((!gfifo2_high)) begin
-            gfifo2_direction <= gfifo2_high;
+always @(posedge wclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO1_RTL_SRL_IN
+    integer ii;
+    if (wr) begin
+        gfifo1_mem[0] <= datain;
+        for (ii=1; ii<16; ii=ii+1) begin
+            gfifo1_mem[ii] <= gfifo1_mem[(ii - 1)];
         end
     end
 end
 
 
 
-assign gfifo2_wrm = (gfifo2_wptr[6] ^ gfifo2_rptr[(6 - 1)]);
-assign gfifo2_wrl = (gfifo2_wptr[(6 - 1)] ^ gfifo2_rptr[6]);
+assign gfifo2_g_fifomem_din = gfifo1_mem[gfifo1_addr];
 
 
-always @(posedge wclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_WRESET_S
-    gfifo2_wrst_s[0] <= (!reset);
-    gfifo2_wrst_s[1] <= gfifo2_wrst_s[0];
-end
 
+assign gfifo1_fbus_rvld = rd1;
 
 
-assign gfifo2_rgnext = ((gfifo2_rbnext >>> 1) ^ gfifo2_rbnext);
-
-
-
-assign gfifo2_wgnext = ((gfifo2_wbnext >>> 1) ^ gfifo2_wbnext);
-
-
-always @(posedge rclk, negedge gfifo2_rrst_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_RPTR_BIN
-    if ((!gfifo2_rrst_n)) begin
-        gfifo2_rbin <= 0;
-        gfifo2_rptr <= 0;
+always @(posedge wclk, posedge reset) begin: M_FIFO_2CLOCK_CASCADE_GFIFO1_RTL_FIFO
+    if (reset == 1) begin
+        fbus1_empty <= 1;
+        fbus1_full <= 0;
+        gfifo1_addr <= 0;
     end
     else begin
-        gfifo2_rbin <= gfifo2_rbnext;
-        gfifo2_rptr <= gfifo2_rgnext;
+        if (gfifo1_fbus_clear) begin
+            gfifo1_addr <= 0;
+            fbus1_empty <= 1'b1;
+            fbus1_full <= 1'b0;
+        end
+        else if ((rd1 && (!wr))) begin
+            fbus1_full <= 1'b0;
+            if ((gfifo1_addr == 0)) begin
+                fbus1_empty <= 1'b1;
+            end
+            else begin
+                gfifo1_addr <= (gfifo1_addr - 1);
+            end
+        end
+        else if ((wr && (!rd1))) begin
+            fbus1_empty <= 1'b0;
+            if ((!fbus1_empty)) begin
+                gfifo1_addr <= (gfifo1_addr + 1);
+            end
+            if (($signed({1'b0, gfifo1_addr}) == (16 - 2))) begin
+                fbus1_full <= 1'b1;
+            end
+        end
     end
 end
 
 
-
-assign fbus2_empty = gfifo2_rempty;
-assign fbus2_full = gfifo2_wfull;
-
-
-always @(rdi, gfifo2_rbin, gfifo2_rempty) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_RPTR_INC
-    if (((!gfifo2_rempty) && rdi)) begin
-        gfifo2_rbnext = ((gfifo2_rbin + 1) % 128);
+always @(posedge wclk, posedge reset) begin: M_FIFO_2CLOCK_CASCADE_GFIFO1_DBG_OCCUPANCY
+    if (reset == 1) begin
+        gfifo1_nvacant <= 16;
+        gfifo1_ntenant <= 0;
     end
     else begin
-        gfifo2_rbnext = gfifo2_rbin;
+        if (gfifo1_fbus_clear) begin
+            gfifo1_nvacant <= 16;
+            gfifo1_ntenant <= 0;
+        end
+        else if ((rd1 && (!wr))) begin
+            gfifo1_nvacant <= (gfifo1_nvacant + 1);
+            gfifo1_ntenant <= (gfifo1_ntenant - 1);
+        end
+        else if ((wr && (!rd1))) begin
+            gfifo1_nvacant <= (gfifo1_nvacant - 1);
+            gfifo1_ntenant <= (gfifo1_ntenant + 1);
+        end
     end
 end
 
 
+always @(posedge rclk, posedge gfifo2_rrst) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_RPTRS
+    integer rbn;
+    integer rpn;
+    if (gfifo2_rrst == 1) begin
+        fbus2_rvld <= 0;
+        gfifo2_rptr <= 0;
+        gfifo2_rbin <= 0;
+        gfifo2_rempty <= 1;
+    end
+    else begin
+        rbn = (gfifo2_rbin + (rd2 && (!gfifo2_rempty)));
+        gfifo2_rbin <= rbn;
+        rpn = ($signed(rbn >>> 1) ^ rbn);
+        gfifo2_rptr <= rpn;
+        gfifo2_rempty <= (rpn == $signed({1'b0, gfifo2_rq2_wptr}));
+        fbus2_rvld <= (rd2 && (!gfifo2_rempty));
+    end
+end
+
+
+always @(posedge wclk, posedge gfifo2_wrst) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_WPTRS
+    integer wbn;
+    integer wpn;
+    if (gfifo2_wrst == 1) begin
+        gfifo2_wfull <= 0;
+        gfifo2_wbin <= 0;
+        gfifo2_wptr <= 0;
+    end
+    else begin
+        wbn = (gfifo2_wbin + (rd1 && (!gfifo2_wfull)));
+        gfifo2_wbin <= wbn;
+        wpn = ($signed(wbn >>> 1) ^ wbn);
+        gfifo2_wptr <= wpn;
+        gfifo2_wfull <= (wpn == {(~gfifo2_wq2_rptr[(7 + 1)-1:(7 - 1)]), gfifo2_wq2_rptr[(7 - 1)-1:0]});
+    end
+end
+
+
+always @(posedge wclk, posedge reset) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_GS1_RTL
+    if (reset == 1) begin
+        gfifo2_gs1_rsync[0] <= 1;
+        gfifo2_gs1_rsync[1] <= 1;
+        gfifo2_wrst <= 1;
+    end
+    else begin
+        gfifo2_gs1_rsync[0] <= reset;
+        gfifo2_gs1_rsync[1] <= gfifo2_gs1_rsync[0];
+        gfifo2_wrst <= gfifo2_gs1_rsync[1];
+    end
+end
+
+
 
 assign gfifo3_fbus_wdata = gfifo2_g_fifomem__dout;
 
 
 always @(posedge rclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_G_FIFOMEM_RTL_RD
-    gfifo2_g_fifomem__dout <= gfifo2_g_fifomem_mem[gfifo2_rptr];
+    gfifo2_g_fifomem__dout <= gfifo2_g_fifomem_mem[gfifo2_raddr];
 end
 
 
 always @(posedge wclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_G_FIFOMEM_RTL_WR
-    gfifo2_g_fifomem__wr <= wr;
-    gfifo2_g_fifomem__addr_w <= gfifo2_wptr;
-    gfifo2_g_fifomem__din <= datain;
+    gfifo2_g_fifomem__wr <= gfifo2__we;
+    gfifo2_g_fifomem__addr_w <= gfifo2_waddr;
+    gfifo2_g_fifomem__din <= gfifo2_g_fifomem_din;
 end
 
 
 end
 
 
-always @(gfifo2_wfull, gfifo2_wbin, wr) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_WPTR_INC
-    if (((!gfifo2_wfull) && wr)) begin
-        gfifo2_wbnext = ((gfifo2_wbin + 1) % 128);
+always @(posedge rclk, posedge reset) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_GS2_RTL
+    if (reset == 1) begin
+        gfifo2_gs2_rsync[0] <= 1;
+        gfifo2_gs2_rsync[1] <= 1;
+        gfifo2_rrst <= 1;
     end
     else begin
-        gfifo2_wbnext = gfifo2_wbin;
+        gfifo2_gs2_rsync[0] <= reset;
+        gfifo2_gs2_rsync[1] <= gfifo2_gs2_rsync[0];
+        gfifo2_rrst <= gfifo2_gs2_rsync[1];
     end
 end
 
 
-
-assign gfifo2_wrst_n = gfifo2_wrst_s[1];
-assign gfifo2_rrst_n = gfifo2_rrst_s[1];
-
-
-always @(posedge rclk, negedge gfifo2_aempty_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_RPTR_EMPTY
-    if ((!gfifo2_aempty_n)) begin
-        gfifo2_rempty <= 1'b1;
-        gfifo2_rempty2 <= 1'b1;
+always @(posedge rclk, posedge gfifo2_rrst) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_GS4_RTL
+    if (gfifo2_rrst == 1) begin
+        gfifo2_rq2_wptr <= 0;
+        gfifo2_gs4_d1 <= 0;
     end
     else begin
-        gfifo2_rempty2 <= (!gfifo2_aempty_n);
-        gfifo2_rempty <= gfifo2_rempty2;
+        gfifo2_gs4_d1 <= gfifo2_wptr;
+        gfifo2_rq2_wptr <= gfifo2_gs4_d1;
     end
 end
 
 
-always @(gfifo2_direction, gfifo2_rptr, gfifo2_wrl, gfifo2_wrm, gfifo2_wptr, gfifo2_wrst_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_ASYNC_CMP_DIR
-    gfifo2_high = 1'b1;
-    if ((gfifo2_wrm && (!gfifo2_wrl))) begin
-        gfifo2_dirset_n = 1'b0;
+
+assign gfifo2__we = (rd1 && (!fbus2_full));
+
+
+
+assign fbus2_empty = gfifo2_rempty;
+assign fbus2_full = gfifo2_wfull;
+
+
+
+assign gfifo2_waddr = gfifo2_wbin[7-1:0];
+assign gfifo2_raddr = gfifo2_rbin[7-1:0];
+
+
+always @(posedge wclk, posedge gfifo2_wrst) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_GS3_RTL
+    if (gfifo2_wrst == 1) begin
+        gfifo2_wq2_rptr <= 0;
+        gfifo2_gs3_d1 <= 0;
     end
     else begin
-        gfifo2_dirset_n = 1'b1;
-    end
-    if ((((!gfifo2_wrm) && gfifo2_wrl) || (!gfifo2_wrst_n))) begin
-        gfifo2_dirclr_n = 1'b0;
-    end
-    else begin
-        gfifo2_dirclr_n = 1'b1;
-    end
-    if (((($signed({1'b0, gfifo2_wptr}) - 1) == gfifo2_rptr) && (!gfifo2_direction))) begin
-        gfifo2_p_aempty_n = 1'b0;
-    end
-    else begin
-        gfifo2_p_aempty_n = 1'b1;
-    end
-    if (((gfifo2_wptr == gfifo2_rptr) && (!gfifo2_direction))) begin
-        gfifo2_aempty_n = 1'b0;
-    end
-    else begin
-        gfifo2_aempty_n = 1'b1;
-    end
-    if (((gfifo2_wptr == gfifo2_rptr) && gfifo2_direction)) begin
-        gfifo2_afull_n = 1'b0;
-    end
-    else begin
-        gfifo2_afull_n = 1'b1;
+        gfifo2_gs3_d1 <= gfifo2_rptr;
+        gfifo2_wq2_rptr <= gfifo2_gs3_d1;
     end
 end
 
 
-always @(posedge wclk, negedge gfifo2_wrst_n, negedge gfifo2_afull_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_WPTR_FULL
-    if ((!gfifo2_wrst_n)) begin
-        gfifo2_wfull <= 1'b0;
-        gfifo2_wfull2 <= 1'b0;
-    end
-    else if ((!gfifo2_afull_n)) begin
-        gfifo2_wfull <= 1'b1;
-        gfifo2_wfull2 <= 1'b1;
-    end
-    else begin
-        gfifo2_wfull <= gfifo2_wfull2;
-        gfifo2_wfull2 <= (!gfifo2_afull_n);
-    end
-end
-
-
-always @(posedge wclk, negedge gfifo2_wrst_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_WPTR_BIN
-    if ((!gfifo2_wrst_n)) begin
-        gfifo2_wbin <= 0;
-        gfifo2_wptr <= 0;
-    end
-    else begin
-        gfifo2_wbin <= gfifo2_wbnext;
-        gfifo2_wptr <= gfifo2_wgnext;
-    end
-end
-
-
-always @(posedge rclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO2_RTL_RRESET_S
-    gfifo2_rrst_s[0] <= (!reset);
-    gfifo2_rrst_s[1] <= gfifo2_rrst_s[0];
-end
-
-
-
-assign fbus2_rvld = (gfifo2__rvld1 && (!gfifo2__rempty));
-
-
 always @(posedge rclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO3_RTL_SRL_IN
     integer ii;
-    if (wri) begin
+    if (wr3) begin
         gfifo3_mem[0] <= gfifo3_fbus_wdata;
         for (ii=1; ii<16; ii=ii+1) begin
             gfifo3_mem[ii] <= gfifo3_mem[(ii - 1)];
             fbus3_empty <= 1'b1;
             fbus3_full <= 1'b0;
         end
-        else if ((rd && (!wri))) begin
+        else if ((rd && (!wr3))) begin
             fbus3_full <= 1'b0;
             if ((gfifo3_addr == 0)) begin
                 fbus3_empty <= 1'b1;
                 gfifo3_addr <= (gfifo3_addr - 1);
             end
         end
-        else if ((wri && (!rd))) begin
+        else if ((wr3 && (!rd))) begin
             fbus3_empty <= 1'b0;
             if ((!fbus3_empty)) begin
                 gfifo3_addr <= (gfifo3_addr + 1);
             gfifo3_nvacant <= 16;
             gfifo3_ntenant <= 0;
         end
-        else if ((rd && (!wri))) begin
+        else if ((rd && (!wr3))) begin
             gfifo3_nvacant <= (gfifo3_nvacant + 1);
             gfifo3_ntenant <= (gfifo3_ntenant - 1);
         end
-        else if ((wri && (!rd))) begin
+        else if ((wr3 && (!rd))) begin
             gfifo3_nvacant <= (gfifo3_nvacant - 1);
             gfifo3_ntenant <= (gfifo3_ntenant + 1);
         end

2014/examples/simple_gemac_core/alt_fifo/m_fifo_short_w11.v

 // File: m_fifo_short_w11.v
 // Generated by MyHDL 0.9dev
-// Date: Tue Jul 15 22:08:27 2014
+// Date: Mon Jul 21 18:53:12 2014
 
 
 `timescale 1ns/10ps

2014/examples/simple_gemac_core/alt_fifo/m_fifo_short_w36.v

 // File: m_fifo_short_w36.v
 // Generated by MyHDL 0.9dev
-// Date: Tue Jul 15 22:08:27 2014
+// Date: Mon Jul 21 18:53:12 2014
 
 
 `timescale 1ns/10ps

2014/examples/simple_gemac_core/test/_sgem_stif.py

                     now(), self.rx_data[36:34], self.rx_data[33], self.rx_data[32],
                     self.rx_data[32:0], word_cnt)) 
 
-                self.pkt_buffer.append(self.rx_data)
+                # need a copy of the value, leave an intbv so it can
+                # be bit sliced later
+                x = intbv(self.rx_data[:])[len(self.rx_data):]
+                self.pkt_buffer.append(x)
                 word_cnt.next = word_cnt + 1
 
         return mon_rx_pkts
         This is a replication of the original testbench send
         packet task.  This should be made genericer in the future!
         
+        data_len is the number of 32 bit words to send, this function
+        is limited to sending multiple of 4 bytes.
+
         36 bit bus
           35:34 : empty bytes (if 4 bytes used == 00)
           33    : end of frame (end of packet), EOF
         # transmit a packet, the packet should be in a Python byte
         # array pkt = array.array('B', ...)
         #txd = int('00' + '0' + '1' + bin(data_start, 32), 2)
+        if data_len < 8:
+            print("@W: minimum payload size 8 words, setting data_len to 8")
+            data_len = 8
+
         txd = concat('00', '0', '1', intbv(data_start)[32:])
         self.tx_data.next = txd
         self.tx_src_rdy.next = True
-        count = 2
+        count = 1
         while count < data_len:
             while not self.tx_dst_rdy:
                 yield self.sys_clk.posedge
             yield self.sys_clk.posedge
-            #print("0x%09X " % (self.tx_data))
-            txd[32:0] = txd[32:0] + 0x01010101
-            count = count + 4
+            #print("@D: TX[%04d]: 0x%09X" % (count, self.tx_data))
+            txd[32:0] = (txd[32:0] + 0x01010101) & 0xFFFFFFFF
+            count = count + 1
             txd[32] = 0
             self.tx_data.next = txd
 
         while not self.tx_dst_rdy:
             yield self.sys_clk.posedge
         yield self.sys_clk.posedge
-        #print("0x%09X " % (self.tx_data))
+        #print("@D: TX[%04d]: 0x%09X" % (count, self.tx_data))
         self.tx_src_rdy.next = False
 
     def t_tx_packet_from_file_sp(self, data_len, nwait=0, fn='test_packet.mem'):
         self.tx_data.next[32] = 1                # SOF
         self.tx_src_rdy.next = True
         yield self.sys_clk.posedge
+        #print("@D: TX[%04d]: 0x%09X" % (0, self.tx_data))
         self.tx_src_rdy.next = False
 
-        for ii in range(4, data_len-3, 4):
+        for ii in range(4, data_len-4, 4):
             while not self.tx_dst_rdy:
                 yield self.sys_clk.posedge
             txd = concat(pkt_mem[ii], pkt_mem[ii+1], pkt_mem[ii+2], pkt_mem[ii+3])
             self.tx_data.next[36:32] = 0
             self.tx_src_rdy.next = True
             yield self.sys_clk.posedge
+            #print("@D: TX[%04d]: 0x%09X" % (ii, self.tx_data))
             self.tx_src_rdy.next = False
 
             for jj in range(nwait):
         # ok, should be at the end of the packet now, if the packet len
         # is not a multiple of four need to indicate the number of empty
         # bytes, this appears to be data_len-ii+1
-        #ii = ii + 4
-        Ne = (data_len-ii) % 4
-        print("@D: last index %d, data_len %d, N %d, Ne %d" % (ii, data_len, N, Ne))
+        ii = ii + 4
+        Ne = (data_len-ii) % 4        
+        #print("@D: last index %d, data_len %d, N %d, Ne %d" % (ii, data_len, N, Ne))
         txd = concat(pkt_mem[ii], pkt_mem[ii+1], pkt_mem[ii+2], pkt_mem[ii+3])
         self.tx_data.next[32:0] = txd
         self.tx_data.next[36:34] = Ne
         self.tx_data.next[32] = 0    # SOF
         self.tx_src_rdy.next = True
         yield self.sys_clk.posedge
+        #print("@D: TX[%04d]: 0x%09X" % (ii, self.tx_data))
         self.tx_src_rdy.next = False
         

2014/examples/simple_gemac_core/test/test_simple_gemac.py

                 # this packet will be recieved
                 pkt_test.next = 1
                 gmii.clear()
-                yield stif.t_tx_packet_sp(0xA0B0C0D0, 10)
-                yield _pause_ticks(100)
+                # @todo: need to debug why the a len less than 4 fails
+                nwords = 1  # number of words in the packet
+                yield stif.t_tx_packet_sp(0xA0B0C0D0, nwords) # received
+                #yield stif.t_tx_packet_sp(0xABBACDDC, nwords)  # dropped
+                # @todo: wait till ?? words recieved or timeout
+                yield _pause_ticks(2000)
                 #gmii.dump_monitors()
-                assert len(gmii.txl) >= 10+8+2  # length of epkt, 8 preamble, 4 crc
-                assert bytes_to_32(gmii.txl, 8) == 0xA0B0C0D0
+                # length of epkt, 8 preamble, 4 crc
+                assert len(gmii.txl) >= 10+8+2, "Incorrect number of bytes transmitted"  
+                assert bytes_to_32(gmii.txl, 8) == 0xA0B0C0D0, "Invalid data transmitted"
                 # @todo: include generic packet checking, preamble, crc, etc
                 # @todo: check the received words in stif.pkt_buffer
+                assert len(stif.pkt_buffer) >= nwords, \
+                    "Invalid number of words received %d" % (len(stif.pkt_buffer))
+                assert stif.pkt_buffer[0][32:] == 0xA0B0C0D0, \
+                    "Invalid received data %08X" % (stif.pkt_buffer[0][32:])
                 stif.clear_rx_packets()
 
                 print("  ~~~ second packet ~~~")
                 yield _pause_ticks(100)
                 # the gmii monitor will capture all bytes (txd), verify
                 # a certain number of bytes recieved
-                assert len(gmii.txl) > 100+8                
-                assert bytes_to_32(gmii.txl, 8) == 0xAABBCCDD
+                assert len(gmii.txl) > 100+8, "Incorrect number of bytes transmitted"
+                assert bytes_to_32(gmii.txl, 8) == 0xAABBCCDD, "Invalid data transmitted"
 
                 yield _pause_ticks(2000)
                 print("  ~~~ third (normal) packet ~~~")
                 pkt_test.next = 3
                 gmii.clear()
-                npkt,nwait = 60,2
-                yield stif.t_tx_packet_from_file_sp(npkt, nwait=nwait)
-                yield _pause_ticks(2000*nwait)
+                yield _pause_ticks(10)
+                nbytes,nwait = 60,0
+                yield stif.t_tx_packet_from_file_sp(nbytes, nwait=nwait)
+                yield _pause_ticks(2000*nwait + 2000)
 
                 # @todo: the number of bytes ethernet preamble+header
                 # the ethernet preamble has 8 bytes, the gmii monitors
                 l1,l2,l3 = len(stif.pkt_mem), len(gmii.txl), len(gmii.rxl)
                 print("  %d, %d, %d" % (l1,l2,l3))
 
-                assert len(gmii.txl) > (npkt+8), "packet not send/recieved"
+                assert len(gmii.txl) > (nbytes+8), "packet not send/recieved"
                 for ii in range(8):
                     print("  xx  %02X  %02X " % (gmii.txl[ii], gmii.rxl[ii]))