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Christopher Felton committed 9f1fbc5

cosim example

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2014/examples/README.md

 considerably faster.
 
 ## Example Model Cosimulation
-If the above worked fine 
+If the above worked fine then change to this directory 
+(gsoc/2014/examples) make sure the myhdl.vpi is copy to this 
+directory and run the "test_cosim.py":
+
+   >> python test_cosim.py
+
+This will use the models from *simmodels.py* and drive a 
+simple Verilog file.  This cosim environment is missing 
+the verification porition, that is checking the output due
+to the stimulus (input) is valid ... that will be left as
+an exercise for the student.

2014/examples/rtp_packetizer.py

+
+from myhdl import *
+
+def m_rtp_packetizer(clock, reset, 
+                     fi_dv, fi_data, fi_full,
+                     fo_dv, fo_data, fo_full):
+
+
+    pad = Signal(intbv(0)[8:])
+    tmp = intbv(0)[24:]
+
+    @always_comb
+    def rtl_assign():
+        fi_full.next = fo_full
+
+    @always_seq(clock.posedge, reset=reset)
+    def rtl():
+        if fi_dv and not fo_full:
+            fo_dv.next = True
+            tmp[:] = ~fi_data
+            fo_data.next = concat(pad, tmp)
+        else:
+            fo_dv.next = False
+            fo_data.next = 0
+
+    return rtl_assign, rtl
+
+
+if __name__ == '__main__':
+
+    clock = Signal(bool(0))
+    reset = ResetSignal(0, active=0, async=True)
+
+    fi_dv = Signal(bool(0))
+    fi_data = Signal(intbv(0)[24:])
+    fi_full = Signal(bool(0))
+
+    fo_dv = Signal(bool(0))
+    fo_data = Signal(intbv(0)[32:])
+    fo_full = Signal(bool(0))
+
+    toVerilog.name = "rtp_packetizer"
+    toVerilog(m_rtp_packetizer, clock, reset, 
+              fi_dv, fi_data, fi_full,
+              fo_dv, fo_data, fo_full)

2014/examples/rtp_packetizer.v

+// File: rtp_packetizer.v
+// Generated by MyHDL 0.9dev
+// Date: Wed Jun 18 07:18:02 2014
+
+
+`timescale 1ns/10ps
+
+module m_rtp_packetizer (
+    clock,
+    reset,
+    fi_dv,
+    fi_data,
+    fi_full,
+    fo_dv,
+    fo_data,
+    fo_full
+);
+
+
+input clock;
+input reset;
+input fi_dv;
+input [23:0] fi_data;
+output fi_full;
+wire fi_full;
+output fo_dv;
+reg fo_dv;
+output [31:0] fo_data;
+reg [31:0] fo_data;
+input fo_full;
+
+wire [7:0] pad;
+
+
+assign pad = 0;
+
+
+
+
+assign fi_full = fo_full;
+
+
+always @(posedge clock, negedge reset) begin: RTP_PACKETIZER_RTL
+    reg [24-1:0] tmp;
+    if (reset == 0) begin
+        fo_data <= 0;
+        fo_dv <= 0;
+        tmp = 0;
+    end
+    else begin
+        if ((fi_dv && (!fo_full))) begin
+            fo_dv <= 1'b1;
+            tmp = (~fi_data);
+            fo_data <= {pad, tmp};
+        end
+        else begin
+            fo_dv <= 1'b0;
+            fo_data <= 0;
+        end
+    end
+end
+
+endmodule

2014/examples/simmodels.py

     def __init__(self):
         self.en = Signal(bool(0))
         self.bytes = Signal(intbv(0)[24:])
-        self.fifo_full = Signal(bool(0))
+        self.full = Signal(bool(0))
         self.clk = Signal(bool(0))
 
     def __str__(self):
-        return "e%d f%d %06X" % (self.en, self.fifo_full, self.bytes)
+        return "VID: e%d f%d %06X" % (self.en, self.full, self.bytes)
 
+class PacketBus(object):
+    def __init__(self):
+        self.en = Signal(bool(0))
+        self.bytes = Signal(intbv(0)[32:])
+        self.full = Signal(bool(0))
+
+    def __str__(self):
+        return "PKT: e%d f%d %08X" % (self.en, self.full, self.bytes)
+
+        
 class UDPBus(object):
     """ ethernet MAC bus interface
     """
             component.
               en:in:
               bytes:in:
-              fifo_full:out: 
+              full:out: 
 
           busout - this is the bus to the downstream component
               en:out: this is the data valid strobe (img_out_en in 
 
               bytes:out: data bus
 
-              fifo_full:in: this is an input indicating the downstream
+              full:in: this is an input indicating the downstream
                 component (the usb controller in 
         """
         assert isinstance(busin, RawVideoBus)
                         self.mem[widx].next = busin.bytes
                         widx.next = widx + 1 if widx < N-1 else 0
 
-                if not busout.fifo_full and ridx != widx:
+                if not busout.full and ridx != widx:
                     print("%08d: [r]  --> %3d,  %3d --> | i:%s, o:%s" % (now(), widx, ridx, str(busin), str(busout)))
                     busout.en.next = True
                     busout.bytes.next = self.mem[ridx]
                     ridx.next = ridx + 1 if ridx < N-1 else 0
 
                 if ((widx+1)%N) == ridx:
-                    busin.fifo_full.next = True
+                    busin.full.next = True
                 else:
-                    busin.fifo_full.next = False
+                    busin.full.next = False
                     
                 # waveform viewer debug
                 _rx.next = ridx

2014/examples/tb_dut.v

+
+module tb_rtp_packetizer;
+   
+   reg clock;
+   reg reset;
+   reg fi_dv;
+   reg [23:0] fi_data;
+   wire       fi_full;
+   wire       fo_dv;
+   wire [31:0] fo_data;
+   reg 	       fo_full;
+
+   initial begin
+      $dumpfile("vcd/_tb_pkt.vcd");
+      $dumpvars(0, tb_rtp_packetizer);      
+   end
+   
+   initial begin
+      $from_myhdl(
+		  clock,
+		  reset,
+		  fi_dv,
+		  fi_data,
+		  fo_full
+		  );
+      $to_myhdl(
+		fi_full,
+		fo_dv,
+		fo_data
+		);
+   end
+   
+   m_rtp_packetizer dut(
+			clock,
+			reset,
+			fi_dv,
+			fi_data,
+			fi_full,
+			fo_dv,
+			fo_data,
+			fo_full
+			);
+   
+endmodule

2014/examples/test_cosim.py

+
+# This file is an example how to 
+
+from __future__ import division
+from __future__ import print_function
+
+import sys
+import os
+import argparse
+from argparse import Namespace
+from array import array
+from random import randint
+
+from myhdl import *
+
+from simmodels import RawVideoBus
+from simmodels import PacketBus
+from simmodels import ImageBuffer
+
+
+def _prep_cosim(args, clock=None, reset=None, intfi=None, intfo=None):
+    """
+    """
+
+    files = ["./rtp_packetizer.v",
+             "./tb_dut.v"]
+
+    print("compiling ...")
+    cmd = "iverilog -o rtp %s " % (" ".join(files))
+    os.system(cmd)
+
+    print("cosimulation setup ...")
+    cmd = "vvp -m ./myhdl.vpi rtp"
+    gcosim = Cosimulation(cmd, 
+                          clock=clock, reset=reset,
+                          fi_dv=intfi.en,
+                          fi_data=intfi.bytes,
+                          fi_full=intfi.full,
+                          fo_dv=intfo.en,
+                          fo_data=intfo.bytes,
+                          fo_full=intfo.full)
+
+    return gcosim
+
+
+def test_packetizer(args):
+    
+    clock = Signal(bool(0))
+    reset = ResetSignal(0, active=0, async=True)
+    busin = RawVideoBus()
+    busraw = RawVideoBus()
+    buspkt = PacketBus()
+
+    tbdut = _prep_cosim(args, clock, reset, busraw, buspkt)
+
+    def _test():
+        imb = ImageBuffer()    
+        tbimg = imb.m_fifo(clock, reset, busin, busraw)
+            
+        @always(delay(3))
+        def tbclk():
+            clock.next = not clock
+
+        @instance
+        def tbstim():
+            reset.next = reset.active
+            yield delay(17)
+            reset.next = not reset.active
+            yield delay(7)
+            yield clock.posedge
+
+            for ii in xrange(23):
+                yield clock.posedge
+                busin.en.next = True
+                busin.bytes.next = randint(0, 2**24-1)
+                
+        
+            raise StopSimulation
+
+        return tbimg, tbclk, tbstim
+
+    if os.path.isfile('vcd/_test.vcd'):
+        os.remove('vcd/_test.vcd')
+
+    traceSignals.timescale = '1ns'
+    traceSignals.name = 'vcd/_test'
+    Simulation((traceSignals(_test), tbdut,)).run()
+
+
+if __name__ == '__main__':
+    args = Namespace()
+    test_packetizer(args)
+