1. Christopher Felton
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Christopher Felton  committed d52c773

tests

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File 2014/examples/simple_gemac_core/alt_fifo/generate_fifos.py

View file
+
+
+from argparse import Namespace
+
+from myhdl import *
+import myhdl_tools as tlz
+
+from m_fifo_2clock_cascade import m_fifo_2clock_cascade
+from m_fifo_short import m_fifo_short
+from m_delay_line import m_delay_line
+
+def convert(args=None):
+    wclk = Signal(bool(0))
+    datain = Signal(intbv(0)[36:])
+    src_rdy_i = Signal(bool(0))
+    dst_rdy_o = Signal(bool(0))
+    space = Signal(intbv(0)[16:])
+    
+    rclk = Signal(bool(0))
+    dataout = Signal(intbv(0)[36:])
+    src_rdy_o = Signal(bool(0))
+    dst_rdy_i = Signal(bool(0))
+    occupied = Signal(intbv(0)[16:])
+
+    reset = ResetSignal(0, active=1, async=True)
+
+
+    toVerilog(m_fifo_2clock_cascade, 
+              wclk, datain, src_rdy_i, dst_rdy_o, space,
+              rclk, dataout, src_rdy_o, dst_rdy_i, occupied,
+              reset)
+
+    clock = Signal(bool(0))
+    clear = Signal(bool(0))
+    datain = Signal(intbv(0)[36:])
+    dataout = Signal(intbv(0)[36:])
+    toVerilog.name = 'm_fifo_short_w36'
+    toVerilog(m_fifo_short,
+              clock, reset, clear,
+              datain, src_rdy_i, dst_rdy_o,
+              dataout, src_rdy_o, dst_rdy_i)
+
+    datain = Signal(intbv(0)[11:])
+    dataout = Signal(intbv(0)[11:])
+    toVerilog.name = 'm_fifo_short_w11'
+    toVerilog(m_fifo_short,
+              clock, reset, clear,
+              datain, src_rdy_i, dst_rdy_o,
+              dataout, src_rdy_o, dst_rdy_i)
+
+
+    delay = Signal(intbv(0, min=0, max=16))
+    di = Signal(intbv(0)[10:])
+    do = Signal(intbv(0)[10:])
+    toVerilog.name = 'm_delay_line_w10'
+    toVerilog(m_delay_line, clock, delay, di, do)
+
+if __name__ == '__main__':
+    convert()

File 2014/examples/simple_gemac_core/alt_fifo/m_delay_line.py

View file
+
+from myhdl import *
+
+def m_delay_line(clk, delay, din, dout):
+
+    dline = [Signal(intbv(0, min=din.min, max=din.max)) for _ in range(16)]
+
+    @always(clk.posedge)
+    def rtl():
+        dline[0].next = din
+        for ii in range(1,16):
+            dline[ii].next = dline[ii-1]
+
+    @always_comb
+    def rtlo():
+        dout.next = dline[delay]
+
+    return rtl, rtlo

File 2014/examples/simple_gemac_core/alt_fifo/m_delay_line.v

View file
+// File: m_delay_line.v
+// Generated by MyHDL 0.9dev
+// Date: Sun Jul  6 05:05:16 2014
+
+
+`timescale 1ns/10ps
+
+module m_delay_line (
+    clk,
+    delay,
+    din,
+    dout
+);
+
+
+input clk;
+input [3:0] delay;
+input [9:0] din;
+output [9:0] dout;
+wire [9:0] dout;
+
+
+reg [9:0] dline [0:16-1];
+
+
+
+
+always @(posedge clk) begin: M_DELAY_LINE_RTL
+    integer ii;
+    dline[0] <= din;
+    for (ii=1; ii<16; ii=ii+1) begin
+        dline[ii] <= dline[(ii - 1)];
+    end
+end
+
+
+
+assign dout = dline[delay];
+
+endmodule

File 2014/examples/simple_gemac_core/alt_fifo/m_delay_line_w10.v

View file
+// File: m_delay_line_w10.v
+// Generated by MyHDL 0.9dev
+// Date: Sun Jul  6 05:10:15 2014
+
+
+`timescale 1ns/10ps
+
+module m_delay_line_w10 (
+    clk,
+    delay,
+    din,
+    dout
+);
+
+
+input clk;
+input [3:0] delay;
+input [9:0] din;
+output [9:0] dout;
+wire [9:0] dout;
+
+
+reg [9:0] dline [0:16-1];
+
+
+
+
+always @(posedge clk) begin: M_DELAY_LINE_W10_RTL
+    integer ii;
+    dline[0] <= din;
+    for (ii=1; ii<16; ii=ii+1) begin
+        dline[ii] <= dline[(ii - 1)];
+    end
+end
+
+
+
+assign dout = dline[delay];
+
+endmodule

File 2014/examples/simple_gemac_core/alt_fifo/m_fifo_2clock_cascade.py

View file
+
+from argparse import Namespace
+
+from myhdl import *
+
+from mn.system import FIFOBus
+from mn.cores.fifo import m_fifo_async
+from mn.cores.fifo import m_fifo_fast
+
+
+def m_fifo_2clock_cascade(
+    wclk,       # in:  write side clock
+    datain,     # in:  write data
+    src_rdy_i,  # in:  
+    dst_rdy_o,  # out: 
+    space,      # out: how many can be written
+    
+    rclk,       # in:  read side clock
+    dataout,    # out: read data
+    src_rdy_o,  # out: 
+    dst_rdy_i,  # in:  
+    occupied,   # out: number in the fifo
+
+    reset,      # in:  system reset
+):
+
+
+    wr = Signal(bool(0))
+    rd = Signal(bool(0))
+    dataout_d = Signal(intbv(0, min=dataout.min, max=dataout.max))
+
+    args = Namespace(width=36, size=128, name='fifo_2clock_cascade')
+    fbus = FIFOBus(args=args)
+    # need to update the fbus refernces to reference the Signals in
+    # the moudule port list (function arguments).
+    fbus.wr = wr
+    fbus.wdata = datain
+    fbus.rd = rd
+    fbus.rdata = dataout_d
+
+    @always_comb
+    def rtl_assign1():
+        wr.next = src_rdy_i & dst_rdy_o
+        rd.next = dst_rdy_i & src_rdy_o
+
+    @always_comb
+    def rtl_assign2():
+        dst_rdy_o.next = not fbus.full
+        src_rdy_o.next = not fbus.empty
+
+    # the original was a chain:
+    #    m_fifo_fast  (16)
+    #    m_fifo_async (??)
+    #    m_fifo_fast  (16)
+    # not sure why the chain was needed
+    gfifo = m_fifo_async(reset, wclk, rclk, fbus)
+    # @todo: calculate space and occupied based on fbus.count
+        
+    # @todo: the output is delayed two clock from the "read" strobe
+    #   the m_fifo_async only has a delta of one (read valid strobe
+    #   aligns with valid data).  Need to delay the data one more
+    #   clock cycle???
+    
+    @always(rclk.posedge)
+    def rtl_delay():
+        dataout.next = dataout_d
+
+    return rtl_assign1, rtl_assign2, gfifo, rtl_delay
+

File 2014/examples/simple_gemac_core/alt_fifo/m_fifo_2clock_cascade.v

View file
+// File: m_fifo_2clock_cascade.v
+// Generated by MyHDL 0.9dev
+// Date: Sun Jul  6 05:10:15 2014
+
+
+`timescale 1ns/10ps
+
+module m_fifo_2clock_cascade (
+    wclk,
+    datain,
+    src_rdy_i,
+    dst_rdy_o,
+    space,
+    rclk,
+    dataout,
+    src_rdy_o,
+    dst_rdy_i,
+    occupied,
+    reset
+);
+
+
+input wclk;
+input [35:0] datain;
+input src_rdy_i;
+output dst_rdy_o;
+wire dst_rdy_o;
+input [15:0] space;
+input rclk;
+output [35:0] dataout;
+reg [35:0] dataout;
+output src_rdy_o;
+wire src_rdy_o;
+input dst_rdy_i;
+input [15:0] occupied;
+input reset;
+
+wire fbus_empty;
+wire [35:0] dataout_d;
+wire rd;
+wire fbus_full;
+wire wr;
+wire gfifo_rrst_n;
+reg gfifo_p_aempty_n;
+reg gfifo_high;
+wire gfifo_fbus_rvld;
+wire [6:0] gfifo_rgnext;
+reg [6:0] gfifo_wbin;
+reg gfifo_wfull;
+wire gfifo_wrl;
+wire gfifo_wrm;
+reg gfifo__rvld1;
+reg gfifo_dirset_n;
+reg [6:0] gfifo_rbin;
+wire gfifo_wrst_n;
+reg gfifo_direction;
+reg gfifo_afull_n;
+reg gfifo_rempty2;
+reg [6:0] gfifo_rbnext;
+reg [6:0] gfifo_wptr;
+reg gfifo_wfull2;
+reg [6:0] gfifo_rptr;
+reg gfifo_dirclr_n;
+reg gfifo_rempty;
+reg gfifo__rempty;
+reg gfifo_aempty_n;
+reg [6:0] gfifo_wbnext;
+wire [6:0] gfifo_wgnext;
+reg [35:0] gfifo_g_fifomem__din;
+reg [6:0] gfifo_g_fifomem__addr_w;
+reg [35:0] gfifo_g_fifomem__dout;
+reg gfifo_g_fifomem__wr;
+
+reg gfifo_rrst_s [0:2-1];
+reg gfifo_wrst_s [0:2-1];
+reg [35:0] gfifo_g_fifomem_mem [0:128-1];
+
+
+
+
+
+assign wr = (src_rdy_i & dst_rdy_o);
+assign rd = (dst_rdy_i & src_rdy_o);
+
+
+
+assign dst_rdy_o = (!fbus_full);
+assign src_rdy_o = (!fbus_empty);
+
+
+always @(posedge rclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_RD_VLD
+    gfifo__rvld1 <= rd;
+    gfifo__rempty <= gfifo_rempty;
+end
+
+
+always @(posedge wclk, negedge gfifo_dirset_n, negedge gfifo_dirclr_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_ASYNC_CMP
+    if ((!gfifo_dirclr_n)) begin
+        gfifo_direction <= 1'b0;
+    end
+    else if ((!gfifo_dirset_n)) begin
+        gfifo_direction <= 1'b1;
+    end
+    else begin
+        if ((!gfifo_high)) begin
+            gfifo_direction <= gfifo_high;
+        end
+    end
+end
+
+
+
+assign gfifo_wrm = (gfifo_wptr[6] ^ gfifo_rptr[(6 - 1)]);
+assign gfifo_wrl = (gfifo_wptr[(6 - 1)] ^ gfifo_rptr[6]);
+
+
+always @(posedge wclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_WRESET_S
+    gfifo_wrst_s[0] <= (!reset);
+    gfifo_wrst_s[1] <= gfifo_wrst_s[0];
+end
+
+
+
+assign gfifo_rgnext = ((gfifo_rbnext >>> 1) ^ gfifo_rbnext);
+
+
+
+assign gfifo_wgnext = ((gfifo_wbnext >>> 1) ^ gfifo_wbnext);
+
+
+always @(posedge rclk, negedge gfifo_rrst_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_RPTR_BIN
+    if ((!gfifo_rrst_n)) begin
+        gfifo_rbin <= 0;
+        gfifo_rptr <= 0;
+    end
+    else begin
+        gfifo_rbin <= gfifo_rbnext;
+        gfifo_rptr <= gfifo_rgnext;
+    end
+end
+
+
+
+assign fbus_empty = gfifo_rempty;
+assign fbus_full = gfifo_wfull;
+
+
+always @(rd, gfifo_rbin, gfifo_rempty) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_RPTR_INC
+    if (((!gfifo_rempty) && rd)) begin
+        gfifo_rbnext = ((gfifo_rbin + 1) % 128);
+    end
+    else begin
+        gfifo_rbnext = gfifo_rbin;
+    end
+end
+
+
+
+assign dataout_d = gfifo_g_fifomem__dout;
+
+
+always @(posedge rclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_G_FIFOMEM_RTL_RD
+    gfifo_g_fifomem__dout <= gfifo_g_fifomem_mem[gfifo_rptr];
+end
+
+
+always @(posedge wclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_G_FIFOMEM_RTL_WR
+    gfifo_g_fifomem__wr <= wr;
+    gfifo_g_fifomem__addr_w <= gfifo_wptr;
+    gfifo_g_fifomem__din <= datain;
+end
+
+
+always @(posedge wclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_G_FIFOMEM_RTL_MEM
+    if (gfifo_g_fifomem__wr) begin
+        gfifo_g_fifomem_mem[gfifo_g_fifomem__addr_w] <= gfifo_g_fifomem__din;
+    end
+end
+
+
+always @(gfifo_wfull, gfifo_wbin, wr) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_WPTR_INC
+    if (((!gfifo_wfull) && wr)) begin
+        gfifo_wbnext = ((gfifo_wbin + 1) % 128);
+    end
+    else begin
+        gfifo_wbnext = gfifo_wbin;
+    end
+end
+
+
+
+assign gfifo_wrst_n = gfifo_wrst_s[1];
+assign gfifo_rrst_n = gfifo_rrst_s[1];
+
+
+always @(posedge rclk, negedge gfifo_aempty_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_RPTR_EMPTY
+    if ((!gfifo_aempty_n)) begin
+        gfifo_rempty <= 1'b1;
+        gfifo_rempty2 <= 1'b1;
+    end
+    else begin
+        gfifo_rempty2 <= (!gfifo_aempty_n);
+        gfifo_rempty <= gfifo_rempty2;
+    end
+end
+
+
+always @(gfifo_direction, gfifo_rptr, gfifo_wrl, gfifo_wrm, gfifo_wptr, gfifo_wrst_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_ASYNC_CMP_DIR
+    gfifo_high = 1'b1;
+    if ((gfifo_wrm && (!gfifo_wrl))) begin
+        gfifo_dirset_n = 1'b0;
+    end
+    else begin
+        gfifo_dirset_n = 1'b1;
+    end
+    if ((((!gfifo_wrm) && gfifo_wrl) || (!gfifo_wrst_n))) begin
+        gfifo_dirclr_n = 1'b0;
+    end
+    else begin
+        gfifo_dirclr_n = 1'b1;
+    end
+    if (((($signed({1'b0, gfifo_wptr}) - 1) == gfifo_rptr) && (!gfifo_direction))) begin
+        gfifo_p_aempty_n = 1'b0;
+    end
+    else begin
+        gfifo_p_aempty_n = 1'b1;
+    end
+    if (((gfifo_wptr == gfifo_rptr) && (!gfifo_direction))) begin
+        gfifo_aempty_n = 1'b0;
+    end
+    else begin
+        gfifo_aempty_n = 1'b1;
+    end
+    if (((gfifo_wptr == gfifo_rptr) && gfifo_direction)) begin
+        gfifo_afull_n = 1'b0;
+    end
+    else begin
+        gfifo_afull_n = 1'b1;
+    end
+end
+
+
+always @(posedge wclk, negedge gfifo_wrst_n, negedge gfifo_afull_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_WPTR_FULL
+    if ((!gfifo_wrst_n)) begin
+        gfifo_wfull <= 1'b0;
+        gfifo_wfull2 <= 1'b0;
+    end
+    else if ((!gfifo_afull_n)) begin
+        gfifo_wfull <= 1'b1;
+        gfifo_wfull2 <= 1'b1;
+    end
+    else begin
+        gfifo_wfull <= gfifo_wfull2;
+        gfifo_wfull2 <= (!gfifo_afull_n);
+    end
+end
+
+
+always @(posedge wclk, negedge gfifo_wrst_n) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_WPTR_BIN
+    if ((!gfifo_wrst_n)) begin
+        gfifo_wbin <= 0;
+        gfifo_wptr <= 0;
+    end
+    else begin
+        gfifo_wbin <= gfifo_wbnext;
+        gfifo_wptr <= gfifo_wgnext;
+    end
+end
+
+
+always @(posedge rclk) begin: M_FIFO_2CLOCK_CASCADE_GFIFO_RTL_RRESET_S
+    gfifo_rrst_s[0] <= (!reset);
+    gfifo_rrst_s[1] <= gfifo_rrst_s[0];
+end
+
+
+
+assign gfifo_fbus_rvld = (gfifo__rvld1 && (!gfifo__rempty));
+
+
+always @(posedge rclk) begin: M_FIFO_2CLOCK_CASCADE_RTL_DELAY
+    dataout <= dataout_d;
+end
+
+endmodule

File 2014/examples/simple_gemac_core/alt_fifo/m_fifo_short.py

View file
+
+from argparse import Namespace
+
+from myhdl import *
+
+from mn.system import FIFOBus
+from mn.cores.fifo import m_fifo_async
+from mn.cores.fifo import m_fifo_fast
+
+
+def m_fifo_short(clock, reset, clear, 
+                 datain, src_rdy_i, dst_rdy_o,
+                 dataout, src_rdy_o, dst_rdy_i):
+
+    wr = Signal(bool(0))
+    rd = Signal(bool(0))
+
+    args = Namespace(width=36, size=16, name='fifo_2clock_cascade')
+    fbus = FIFOBus(args=args)
+    # need to update the fbus refernces to reference the Signals in
+    # the moudule port list (function arguments).
+    fbus.wr = wr
+    fbus.wdata = datain
+    fbus.rd = rd
+    fbus.rdata = dataout
+    fbus.clear = clear
+
+    @always_comb
+    def rtl_assign1():
+        wr.next = src_rdy_i & dst_rdy_o
+        rd.next = dst_rdy_i & src_rdy_o
+
+    @always_comb
+    def rtl_assign2():
+        dst_rdy_o.next = not fbus.full
+        src_rdy_o.next = not fbus.empty
+
+    gfifo = m_fifo_fast(clock, reset, fbus)
+
+    return rtl_assign1, rtl_assign2, gfifo
+    

File 2014/examples/simple_gemac_core/alt_fifo/m_fifo_short_w11.v

View file
+// File: m_fifo_short_w11.v
+// Generated by MyHDL 0.9dev
+// Date: Sun Jul  6 05:10:15 2014
+
+
+`timescale 1ns/10ps
+
+module m_fifo_short_w11 (
+    clock,
+    reset,
+    clear,
+    datain,
+    src_rdy_i,
+    dst_rdy_o,
+    dataout,
+    src_rdy_o,
+    dst_rdy_i
+);
+
+
+input clock;
+input reset;
+input clear;
+input [10:0] datain;
+input src_rdy_i;
+output dst_rdy_o;
+wire dst_rdy_o;
+output [10:0] dataout;
+wire [10:0] dataout;
+output src_rdy_o;
+wire src_rdy_o;
+input dst_rdy_i;
+
+reg fbus_empty;
+wire rd;
+wire wr;
+reg fbus_full;
+reg [4:0] gfifo_nvacant;
+reg [3:0] gfifo_addr;
+wire gfifo_fbus_rvld;
+reg [4:0] gfifo_ntenant;
+
+reg [35:0] gfifo_mem [0:16-1];
+
+
+
+
+
+assign wr = (src_rdy_i & dst_rdy_o);
+assign rd = (dst_rdy_i & src_rdy_o);
+
+
+
+assign dst_rdy_o = (!fbus_full);
+assign src_rdy_o = (!fbus_empty);
+
+
+always @(posedge clock) begin: M_FIFO_SHORT_W11_GFIFO_RTL_SRL_IN
+    integer ii;
+    if (wr) begin
+        gfifo_mem[0] <= datain;
+        for (ii=1; ii<16; ii=ii+1) begin
+            gfifo_mem[ii] <= gfifo_mem[(ii - 1)];
+        end
+    end
+end
+
+
+
+assign dataout = gfifo_mem[gfifo_addr];
+
+
+
+assign gfifo_fbus_rvld = rd;
+
+
+always @(posedge clock, posedge reset) begin: M_FIFO_SHORT_W11_GFIFO_RTL_FIFO
+    if (reset == 1) begin
+        fbus_empty <= 1;
+        fbus_full <= 0;
+        gfifo_addr <= 0;
+    end
+    else begin
+        if (clear) begin
+            gfifo_addr <= 0;
+            fbus_empty <= 1'b1;
+            fbus_full <= 1'b0;
+        end
+        else if ((rd && (!wr))) begin
+            fbus_full <= 1'b0;
+            if ((gfifo_addr == 0)) begin
+                fbus_empty <= 1'b1;
+            end
+            else begin
+                gfifo_addr <= (gfifo_addr - 1);
+            end
+        end
+        else if ((wr && (!rd))) begin
+            fbus_empty <= 1'b0;
+            if ((!fbus_empty)) begin
+                gfifo_addr <= (gfifo_addr + 1);
+            end
+            if (($signed({1'b0, gfifo_addr}) == (16 - 2))) begin
+                fbus_full <= 1'b1;
+            end
+        end
+    end
+end
+
+
+always @(posedge clock, posedge reset) begin: M_FIFO_SHORT_W11_GFIFO_DBG_OCCUPANCY
+    if (reset == 1) begin
+        gfifo_nvacant <= 16;
+        gfifo_ntenant <= 0;
+    end
+    else begin
+        if (clear) begin
+            gfifo_nvacant <= 16;
+            gfifo_ntenant <= 0;
+        end
+        else if ((rd && (!wr))) begin
+            gfifo_nvacant <= (gfifo_nvacant + 1);
+            gfifo_ntenant <= (gfifo_ntenant - 1);
+        end
+        else if ((wr && (!rd))) begin
+            gfifo_nvacant <= (gfifo_nvacant - 1);
+            gfifo_ntenant <= (gfifo_ntenant + 1);
+        end
+    end
+end
+
+endmodule

File 2014/examples/simple_gemac_core/alt_fifo/m_fifo_short_w36.v

View file
+// File: m_fifo_short_w36.v
+// Generated by MyHDL 0.9dev
+// Date: Sun Jul  6 05:10:15 2014
+
+
+`timescale 1ns/10ps
+
+module m_fifo_short_w36 (
+    clock,
+    reset,
+    clear,
+    datain,
+    src_rdy_i,
+    dst_rdy_o,
+    dataout,
+    src_rdy_o,
+    dst_rdy_i
+);
+
+
+input clock;
+input reset;
+input clear;
+input [35:0] datain;
+input src_rdy_i;
+output dst_rdy_o;
+wire dst_rdy_o;
+output [35:0] dataout;
+wire [35:0] dataout;
+output src_rdy_o;
+wire src_rdy_o;
+input dst_rdy_i;
+
+reg fbus_empty;
+wire rd;
+wire wr;
+reg fbus_full;
+reg [4:0] gfifo_nvacant;
+reg [3:0] gfifo_addr;
+wire gfifo_fbus_rvld;
+reg [4:0] gfifo_ntenant;
+
+reg [35:0] gfifo_mem [0:16-1];
+
+
+
+
+
+assign wr = (src_rdy_i & dst_rdy_o);
+assign rd = (dst_rdy_i & src_rdy_o);
+
+
+
+assign dst_rdy_o = (!fbus_full);
+assign src_rdy_o = (!fbus_empty);
+
+
+always @(posedge clock) begin: M_FIFO_SHORT_W36_GFIFO_RTL_SRL_IN
+    integer ii;
+    if (wr) begin
+        gfifo_mem[0] <= datain;
+        for (ii=1; ii<16; ii=ii+1) begin
+            gfifo_mem[ii] <= gfifo_mem[(ii - 1)];
+        end
+    end
+end
+
+
+
+assign dataout = gfifo_mem[gfifo_addr];
+
+
+
+assign gfifo_fbus_rvld = rd;
+
+
+always @(posedge clock, posedge reset) begin: M_FIFO_SHORT_W36_GFIFO_RTL_FIFO
+    if (reset == 1) begin
+        fbus_empty <= 1;
+        fbus_full <= 0;
+        gfifo_addr <= 0;
+    end
+    else begin
+        if (clear) begin
+            gfifo_addr <= 0;
+            fbus_empty <= 1'b1;
+            fbus_full <= 1'b0;
+        end
+        else if ((rd && (!wr))) begin
+            fbus_full <= 1'b0;
+            if ((gfifo_addr == 0)) begin
+                fbus_empty <= 1'b1;
+            end
+            else begin
+                gfifo_addr <= (gfifo_addr - 1);
+            end
+        end
+        else if ((wr && (!rd))) begin
+            fbus_empty <= 1'b0;
+            if ((!fbus_empty)) begin
+                gfifo_addr <= (gfifo_addr + 1);
+            end
+            if (($signed({1'b0, gfifo_addr}) == (16 - 2))) begin
+                fbus_full <= 1'b1;
+            end
+        end
+    end
+end
+
+
+always @(posedge clock, posedge reset) begin: M_FIFO_SHORT_W36_GFIFO_DBG_OCCUPANCY
+    if (reset == 1) begin
+        gfifo_nvacant <= 16;
+        gfifo_ntenant <= 0;
+    end
+    else begin
+        if (clear) begin
+            gfifo_nvacant <= 16;
+            gfifo_ntenant <= 0;
+        end
+        else if ((rd && (!wr))) begin
+            gfifo_nvacant <= (gfifo_nvacant + 1);
+            gfifo_ntenant <= (gfifo_ntenant - 1);
+        end
+        else if ((wr && (!rd))) begin
+            gfifo_nvacant <= (gfifo_nvacant - 1);
+            gfifo_ntenant <= (gfifo_ntenant + 1);
+        end
+    end
+end
+
+endmodule

File 2014/examples/simple_gemac_core/simple_gemac/build

View file
     'miim/eth_outputcontrol.v',
     'miim/eth_shiftreg.v',
 
-
     # myhdl fifo replacements
     '../alt_fifo/m_fifo_2clock_cascade.v',
-    '../alt_fifo/m_fifo_short.v',
-    '../alt_fifo/m_delay_line.v',
+    '../alt_fifo/m_fifo_short_w36.v',
+    '../alt_fifo/m_fifo_short_w11.v',
+    '../alt_fifo/m_delay_line_w10.v',
 
     'll8_shortfifo.v',
     'll8_to_fifo36.v',

File 2014/examples/simple_gemac_core/simple_gemac/ll8_shortfifo.v

View file
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    11:46:55 02/18/2011 
-// Design Name: 
-// Module Name:    ll8_shortfifo 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module ll8_shortfifo
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:46:55 02/18/2011 
+// Design Name: 
+// Module Name:    ll8_shortfifo 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ll8_shortfifo
   (input clk, input reset, input clear,
    input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o,
    output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i);
 
-   fifo_short #(.WIDTH(11)) fifo_short
-     (.clk(clk), .reset(reset), .clear(clear),
+   //fifo_short #(.WIDTH(11)) fifo_short
+   //  (.clk(clk), .reset(reset), .clear(clear),
+   //   .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+   //   .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+
+   m_fifo_short_w11 u_fifo_short
+     (.clock(clk), .reset(reset), .clear(clear),
       .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
-      .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
-
-
-endmodule
+      .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+
+
+
+endmodule

File 2014/examples/simple_gemac_core/simple_gemac/simple_gemac_rx.v

View file
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    11:28:29 02/18/2011 
-// Design Name: 
-// Module Name:    simple_gemac_rx 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-module simple_gemac_rx (
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:28:29 02/18/2011 
+// Design Name: 
+// Module Name:    simple_gemac_rx 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module simple_gemac_rx (
   input reset,
    input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
    output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
    wire calc_crc 	 = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
 
    localparam DELAY  = 4'd6;
-   delay_line #(.WIDTH(10)) rx_delay
-     (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del}));
+   m_delay_line_w10  u_rx_delay
+     (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}), .dout({rx_dv_del,rx_er_del,rxd_del}));
 
    always @(posedge rx_clk)
      if(reset)
    assign rx_clk 	  = GMII_RX_CLK;
 
    assign debug = rx_state;
-
-
-endmodule
+
+
+endmodule

File 2014/examples/simple_gemac_core/simple_gemac/simple_gemac_wrapper.v

View file
-
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    11:38:55 02/18/2011 
-// Design Name: 
-// Module Name:    simple_gemac_wrapper 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description:
-//
-// GEMAC wrapper
-// FIFOs convert 36-bit data to four 8-bit words. Extra control signals are:
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:38:55 02/18/2011 
+// Design Name: 
+// Module Name:    simple_gemac_wrapper 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description:
+//
+// GEMAC wrapper
+// FIFOs convert 36-bit data to four 8-bit words. Extra control signals are:
 // f36_sof = f36_data[32];
 // f36_eof = f36_data[33];
-// f36_occ = f36_data[35:34];
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
+// f36_occ = f36_data[35:34];
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
 
 module simple_gemac_wrapper
   #(parameter RXFIFOSIZE=9,
    wire 	  tx_reset, rx_reset;
    reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
    reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
-	wire [39:0] simple_gemac_debug;
+	wire [39:0] simple_gemac_debug;
 
    simple_gemac simple_gemac
      (.clk125(clk125),  .reset(reset),
       .rx_clk(rx_clk), .rx_data(rx_data),
       .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
       .tx_clk(tx_clk), .tx_data(tx_data), 
-      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
 		.debug(simple_gemac_debug)
       );
-   
+   
 	
    simple_gemac_wb simple_gemac_wb
      (.wb_clk(wb_clk), .wb_rst(wb_rst),
       .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
       .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
 
-   fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
+   m_fifo_2clock_cascade  u_rx_2clk_fifo
      (.wclk(rx_clk), .datain(rx_f36_data_int1), 
       .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
       .rclk(sys_clk), .dataout(rx_f36_data), 
-      .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
+      .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), 
+      .occupied(), 
+      .reset(reset));
    
    // TX FIFO Chain
    wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
    wire [35:0] 	  tx_f36_data_int1;
    wire 	  tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
    
-   fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
+   m_fifo_2clock_cascade u_tx_2clk_fifo
      (.wclk(sys_clk), .datain(tx_f36_data), 
       .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
       .rclk(tx_clk), .dataout(tx_f36_data_int1), 
-      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
-   
-	// Converts 36-bit word to 4*8 bit outpus plus control signals
-	wire [2:0] fifo36_to_ll8_debug;
+      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), 
+      .occupied(), 
+      .reset(reset));
+   
+   // Converts 36-bit word to 4*8 bit outpus plus control signals
+   wire [2:0] 	  fifo36_to_ll8_debug;
    fifo36_to_ll8 fifo36_to_ll8
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
       .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
-      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n),
+      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n),
 		.debug(fifo36_to_ll8_debug));
 
    assign tx_ll_sof2 	    = ~tx_ll_sof2_n;
       .error_i(1'b0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
       .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
       .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
-   
+   
 	wire [2:0] ll8_to_txmac_xferstate;
    ll8_to_txmac ll8_to_txmac
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
       .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
-      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
 		.debug(ll8_to_txmac_xferstate));
-
+
 	// Flow control
    flow_ctrl_rx flow_ctrl_rx
      (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
       .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
       .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
    
-   
-	// Debug signals
-	wire [79:0] debug_tx;
-	wire [31:0]	debug_rx;
+   
+	// Debug signals
+	wire [79:0] debug_tx;
+	wire [31:0]	debug_rx;
 	
    assign debug_tx  = { tx_f36_data_int1[31:0], fifo36_to_ll8_debug, simple_gemac_debug[39:32], {reset, tx_reset, ll8_to_txmac_xferstate}, { tx_ll_data },
 			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
 			{ rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
 			{ rx_data} };
 
-   assign debug  = debug_tx;
+   assign debug  = debug_tx;
 
 endmodule // simple_gemac_wrapper

File 2014/examples/simple_gemac_core/test/_gemac_filelist.py

View file
+
+
+filelist = [
+
+    '../simple_gemac/miim/eth_miim.v',
+    '../simple_gemac/miim/eth_clockgen.v',
+    '../simple_gemac/miim/eth_outputcontrol.v',
+    '../simple_gemac/miim/eth_shiftreg.v',
+
+    # myhdl fifo replacements
+    '../alt_fifo/m_fifo_2clock_cascade.v',
+    '../alt_fifo/m_fifo_short_w36.v',
+    '../alt_fifo/m_fifo_short_w11.v',
+    '../alt_fifo/m_delay_line_w10.v',
+
+    '../simple_gemac/ll8_shortfifo.v',
+    '../simple_gemac/ll8_to_fifo36.v',
+    '../simple_gemac/fifo36_to_ll8.v',
+    '../simple_gemac/ll8_to_txmac.v',
+    '../simple_gemac/rxmac_to_ll8.v',
+    '../simple_gemac/oneshot_2clk.v',
+    '../simple_gemac/reset_sync.v',
+    '../simple_gemac/crc.v',
+    '../simple_gemac/address_filter.v',
+    '../simple_gemac/flow_ctrl_rx.v',
+    '../simple_gemac/flow_ctrl_tx.v',
+    '../simple_gemac/simple_gemac_rx.v',
+    '../simple_gemac/simple_gemac_tx.v',
+    '../simple_gemac/simple_gemac_wb.v',
+    '../simple_gemac/simple_gemac.v',
+    '../simple_gemac/simple_gemac_wrapper.v',
+    
+    ]

File 2014/examples/simple_gemac_core/test/tb_simple_gemac.v

View file
+
+module tb_simple_gemac;
+
+   /*input */  reg  clk125;             
+   /*input */  reg  reset;
+   // GMII
+   /*output*/  wire GMII_GTX_CLK  ;
+   /*output*/  wire GMII_TX_EN 	  ;
+   /*output*/  wire GMII_TX_ER 	  ;
+   /*output*/  wire [7:0] GMII_TXD;
+   /*input */  reg  GMII_RX_CLK	  ;
+   /*input */  reg  GMII_RX_DV 	  ;
+   /*input */  reg  GMII_RX_ER 	  ;
+   /*input */  reg  [7:0] GMII_RXD;
+    
+    // Client FIFO Interfaces
+    /*input */ reg  sys_clk           ;
+    /*output*/ wire [35:0] rx_f36_data;
+    /*output*/ wire rx_f36_src_rdy    ;
+    /*input */ reg  rx_f36_dst_rdy    ;
+    /*input */ reg  [35:0] tx_f36_data;
+    /*input */ reg  tx_f36_src_rdy    ;
+    /*output*/ wire tx_f36_dst_rdy    ;   
+    
+    // Wishbone Interface
+    /*input */ reg  wb_clk         ;
+    /*input */ reg  wb_rst 	   ;
+    /*input */ reg  wb_stb 	   ;
+    /*input */ reg  wb_cyc 	   ;
+    /*output*/ wire wb_ack 	   ;
+    /*input */ reg  wb_we	   ;
+    /*input */ reg  [7:0] wb_adr   ;
+    /*input */ reg  [31:0] wb_dat_i;
+    /*output*/ wire [31:0] wb_dat_o;
+    
+   // MIIM
+   /*inout */  wire mdio;   
+   /*output*/  wire mdc;   
+   /*output*/  wire [79:0] debug;       
+   
+   initial begin
+      $dumpfile("vcd/_tb_simpe_gemac.vcd");
+      $dumpvars(0, tb_simple_gemac);
+   end
+
+   initial begin
+      $from_myhdl(
+	 clk125, reset,
+	 GMII_RX_CLK, GMII_RX_DV, GMII_RX_ER, GMII_RXD,
+	 sys_clk,
+	 rx_f36_dst_rdy, tx_f36_data, tx_f36_src_rdy,
+	 wb_clk, wb_rst, wb_stb, wb_cyc, wb_we, wb_adr,
+	 wb_dat_i
+	 );
+      
+      $to_myhdl(
+	 GMII_GTX_CLK, GMII_TX_EN, GMII_TX_ER, GMII_TXD,
+	 rx_f36_data, rx_f36_src_rdy, tx_f36_dst_rdy,
+	 wb_ack, wb_dat_o
+	 );
+   end
+   
+   simple_gemac_wrapper 
+     DUT
+       (.clk125              (clk125           ),   /*input */
+	.reset               (reset            ),   /*input */            
+	// ethernet phy interface   		    
+	.GMII_GTX_CLK        (GMII_GTX_CLK     ),   /*output*/  
+	.GMII_TX_EN          (GMII_TX_EN       ),   /*output*/  
+	.GMII_TX_ER          (GMII_TX_ER       ),   /*output*/  
+	.GMII_TXD            (GMII_TXD         ),   /*output*/  
+	.GMII_RX_CLK         (GMII_RX_CLK      ),   /*input */  
+	.GMII_RX_DV          (GMII_RX_DV       ),   /*input */  
+	.GMII_RX_ER          (GMII_RX_ER       ),   /*input */  
+	.GMII_RXD            (GMII_RXD         ),   /*input */  
+	// streaming interfaces          
+	.sys_clk             (sys_clk          ),   /*input */
+	.rx_f36_data         (rx_f36_data      ),   /*output*/
+	.rx_f36_src_rdy      (rx_f36_src_rdy   ),   /*output*/
+	.rx_f36_dst_rdy      (rx_f36_dst_rdy   ),   /*input */
+	.tx_f36_data         (tx_f36_data      ),   /*input */
+	.tx_f36_src_rdy      (tx_f36_src_rdy   ),   /*input */
+	.tx_f36_dst_rdy      (tx_f36_dst_rdy   ),   /*output*/
+	// wishbone interface              
+	.wb_clk              (wb_clk           ),   /*input */ 
+	.wb_rst              (wb_rst           ),   /*input */
+	.wb_stb              (wb_stb           ),   /*input */
+	.wb_cyc              (wb_cyc           ),   /*input */
+	.wb_ack              (wb_ack           ),   /*output*/
+	.wb_we               (wb_we            ),   /*input */
+	.wb_adr              (wb_adr           ),   /*input */
+	.wb_dat_i            (wb_dat_i         ),   /*input */
+	.wb_dat_o            (wb_dat_o         ),   /*output*/
+	//                   
+	.mdio                (mdio             ),   /*inout */            
+	.mdc                 (mdc              ),   /*output*/             
+	.debug               (debug            )    /*output*/
+	);
+       	
+     
+endmodule

File 2014/examples/simple_gemac_core/test/test_simple_gemac.py

View file
+
+from __future__ import division
+from __future__ import print_function
+
+import sys
+import os
+import argparse
+from argparse import Namespace
+from array import array
+
+from myhdl import *
+
+from mn.system import Wishbone
+
+from _gemac_filelist import filelist
+
+
+class GMII(object):
+    def __init__(self):
+        # outputs (from DUT)
+        self.tx_clk = Signal(bool(0))
+        self.tx_en = Signal(bool(0))
+        self.tx_er = Signal(bool(0))
+        self.txd = Signal(intbv(0)[8:])
+        
+        # inputs (to DUT)
+        self.rx_clk = Signal(bool(0))
+        self.rx_dv = Signal(bool(0))
+        self.rx_er = Signal(bool(0))
+        self.rxd = Signal(intbv(0)[8:])
+
+class StreamIntf(object):
+    def __init__(self, W=36):
+        # out of 
+        self.rx_data = Signal(intbv(0)[W:])
+        self.rx_src_rdy = Signal(bool(0))
+        self.rx_dst_rdy = Signal(bool(0))
+        
+        # into
+        self.tx_data = Signal(intbv(0)[W:])
+        self.tx_src_rdy = Signal(bool(0))
+        self.tx_dst_rdy = Signal(bool(0))
+
+    def m_rx_packets(self, clock, reset):
+        # recieve packets into a buffer
+        pass
+
+    def t_tx_packet(self, pkt):
+        # transmit a packet, the packet should be in a Python byte
+        # array pkt = array.array('B', ...)
+        pass
+
+
+#=====================================================================
+def _prep_cosim(
+    args,
+    clk125=None,
+    reset=None,
+    gmii=None,
+    sys_clk=None,
+    stintf=None,
+    wb=None,
+    #mdio=None,
+    #mdc=None            
+):
+    """
+    """
+    global filelist
+    files = filelist + ['tb_simple_gemac.v']
+    print("compiling ...")
+    cmd = "iverilog -o simple_gemac %s " % (" ".join(files))
+    os.system(cmd)
+
+    if not os.path.exists('vcd'):
+        os.makedirs('vcd')
+
+    print("cosimulation setup ...")
+    cmd = "vvp -m ../myhdl.vpi simple_gemac"
+
+    gcosim = Cosimulation(cmd,
+        clk125=clk125, 
+        reset=reset,
+        # ethernet phy interface
+        GMII_GTX_CLK=gmii.tx_clk, 
+        GMII_TX_EN=gmii.tx_en, 
+        GMII_TX_ER=gmii.tx_er, 
+        GMII_TXD=gmii.txd,
+        GMII_RX_CLK=gmii.rx_clk, 
+        GMII_RX_DV=gmii.rx_dv, 
+        GMII_RX_ER=gmii.rx_er, 
+        GMII_RXD=gmii.rxd,
+        # internal logic 
+        sys_clk=sys_clk,
+        rx_f36_data=stintf.rx_data, 
+        rx_f36_src_rdy=stintf.rx_src_rdy, 
+        rx_f36_dst_rdy=stintf.rx_dst_rdy,
+        tx_f36_data=stintf.tx_data, 
+        tx_f36_src_rdy=stintf.tx_src_rdy, 
+        tx_f36_dst_rdy=stintf.tx_dst_rdy,
+
+        # wishbone interface (device perspective)
+        wb_clk=wb.clk_i,
+        wb_rst=wb.rst_i,
+        wb_stb=wb.stb_i,
+        wb_cyc=wb.cyc_i,
+        wb_ack=wb.ack_o,
+        wb_we=wb.we_i,
+        wb_adr=wb.adr_i,
+        wb_dat_i=wb.dat_i,
+        wb_dat_o=wb.dat_o
+
+        # miim
+        #mdio=mdi, mdc=mdc 
+    )
+
+    return gcosim
+
+#=====================================================================
+def test_simple_gemac(args):
+    
+
+    # clocks
+    clk125 = Signal(bool(0))
+    sys_clk = Signal(bool(0))
+    clock = sys_clk
+    reset = ResetSignal(0, active=1, async=True)
+
+    # intefaces
+    gmii = GMII()
+    stintf = StreamIntf()
+    wb = Wishbone(clock=sys_clk, reset=reset)
+
+    tbdut = _prep_cosim(args, clk125, reset, gmii, 
+                        sys_clk, stintf, wb)
+    
+    
+    def _test():
+        
+        # note the time scale is 1ns/1ps (1ps)
+        @always(delay(4000))
+        def tbclk1():
+            clk125.next = not clk125
+
+        @always(delay(10000))
+        def tbclk2():
+            clk_sys.next = not clk_sys
+
+
+        @instance
+        def tbstim():
+            yield delay(13)
+            reset.next = reset.active
+            yield delay(33)
+            reset.next = not reset.active
+            yield clock.posedge
+
+            raise StopSimulation
+
+        return tbclk1, tbclk2, tbstim
+
+    traceSignals.timescale = '1ps'
+    traceSignals.name = 'vcd/_test'
+    fn = trancSignals.name + '.vcd'
+    if os.path.isfile(fn):
+        os.remove(fn)
+
+    Simulation((traceSignals(_test), tbdut,)).run()
+
+
+#=====================================================================
+if __name__ == '__main__':
+    args = Namespace()
+    test_simple_gemac(args)