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Christopher Felton  committed 3d8addb

solution

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  • Parent commits b5682fa

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Files changed (2)

+
+
+from myhdl import *
+
+def m_shifty(clock, reset, load, lval, obit, ival=0):
+    
+    y = Signal(intbv(ival, min=lval.min, max=lval.max))
+    mb = len(y)-1
+
+    @always_seq(clock.posedge, reset=reset)
+    def rtl():
+        if load:
+            y.next = lval
+        else:
+            y.next = concat(y[mb-1:0], y[mb]) 
+
+    @always_comb
+    def rtl_assign():
+        obit.next = y[mb]
+
+    m_shifty.y = y
+
+    return rtl, rtl_assign

File test_01_mex.py

 from myhdl import *
 from myhdl_tools import Clock, Reset
 
+from _z01 import m_shifty
+
 def test(mod):
     clock = Clock(0)
     reset = Reset(0, active=0, async=True)
         tbdut = mod(clock, reset, load, lval, obit, ival=ival)
         tbclk = clock.gen()
 
-        log = [(-1,0,0,0,0,) for _ in range(4)]
-        isht = intbv(0, max=256, min=0)
+        log = [(-1,0,0,0,0,) for _ in range(20)]
+        isht = Signal(intbv(0, max=256, min=0))
+
         @always(clock.posedge)
+        def tbmon():
+            log.append((now(), load, lval, obit, mod.y,))
+            log.pop(0)
+            
         @instance
         def tbstim():
             try:
-                isht[:] = ival
+                isht.next = ival
                 yield reset.pulse(10)
                 yield clock.posedge
 
                 for ii in xrange(1000):
-                    log.append((now(), load, lval, obit, mod.y,))
-                    log.pop(0)
                     assert isht[7] == obit
-                    isht[:] = concat(isht[6:0], isht[7])
+                    isht.next = concat(isht[6:0], isht[7])
+                    yield clock.posedge
 
-                for ii in range(333):
+                for ii in range(33):
+                    rr = randint(1, lval.max-1)
+                    lval.next = rr
+                    load.next = True
+                    isht.next = rr
+                    yield clock.posedge
+                    load.next = False  
+                    yield clock.posedge                  
                     for ii in xrange(1000):
-                        log.append((now(), load, lval, obit, mod.y,))
-                        log.pop(0)
+                        assert isht[7] == obit
+                        isht.next = concat(isht[6:0], isht[7])
+                        yield clock.posedge
                         
                 print("Test Successful")
             except Exception, err:
                 yield delay(10)
                 print("Test Error")
-                print("Last five clock cycles")
-                print(" time    | load | lval  | obit | ")
+                print("Last %d clock cycles" % (len(log)))
+                print(" time    | load | lval | obit | shift (y)")
                 for ee in log:
-                    print("%8d | %4d | %04X | %d | %04X" % ee)
+                    print("%8d | %4d | %04X | %4d | %04X" % ee)
                 print(err)
 
             raise StopSimulation
 
-        return tbclk, tbdut, tbstim
+        return tbclk, tbdut, tbstim, tbmon
 
     traceSignals.name = 'vcd/01_mex'
     if os.path.isfile(traceSignals.name+'.vcd'):
     
     Simulation(traceSignals(_test)).run()
     toVHDL(mod, clock, reset, load, lval, obit, ival=ival)
-    toVerilog(mod, clock, reset, load, lval, obit, ival=ival)
+    toVerilog(mod, clock, reset, load, lval, obit, ival=ival)
+
+if __name__ == '__main__':
+    test(m_shifty)