1. Christopher Felton
  2. myhdl_tests




This repo contains a set of myhdl tests to help debug / test issues that have been discussed on the mailing list.

py.test is used to run the tests, simply clone the repo to a local directory. Change to the directory and run:

>> hg clone https://cfelton@bitbucket.org/cfelton/myhdl_tests

>> py.test

This will execute all the tests. To execute a single test:

>> py.test test_<name>.py

Specific simuators can be choosen as well:

>> py.test --sim ghdl

>> py.test --sim icarus

>> py.test --sim all # default

Use the following to supress the "traceback" dumps at the end (I typically will run the single failing test to analyze, the tracebacks make it hard to see what failed):

>> py.test --tb=no

Also, sometimes it is useful to stop on error, mainly because the generated V* files can be overwritten:

>> py.test -x

These test mainly test conversion to Verilog and VHDL. These tests use the testbench conversion to create a testbench in the target language. Then a V* simulator is run and monitored for success. A loose coding convetion is used in the tests:

  • mod_* : these are the myhdl modules to be converted and they contain the feature to be tested.
  • tb_* : These are the converible testbenchs, the testbenches need to be convertible. Only the convertible subset can be used for testing.
  • test_* : This is the entry function, a simulator class will be provided through the py.test parameters. These will call the /simulator/ object and convert the testbenches and modules.

List of current tests

The following is a brief description of the tests and a possible fix. These are all tested against the 0.8dev branch.


This tests the VHDL conversion and the the different single bit operations. There was a reported error with multiply.


There is no error here, there were five cases outlined that were expected to be supported:

  1. if not sig
  2. if sig == False
  3. if sig == bool(0) # should be the same as #2
  4. if sig == 0
  5. if sig == intbv(0)

The first four are supported when using:

def hdl():
   if <cases 1-4>


def hdl():
   if <cases 1-4>

The error does show up in VHDL conversion when the different conditionals are used in testing the reset:

@always(clock.posedge, reset.negedge)
def hdl():
   if <cases 1-3> # fail

For the reset #4 is used as described in the MyHDL manual. This is not really an error as discussed on the mailing list.

Number five I didn't include because it is more of the mixing bool and intbv[1:], a separate issues.


This tests the error case when more than 2 operands are in an expression.


These test the mixing of bool and intbv[1:]