me = 0

class Interface:
    def __init__(self):
        self.x = Signal(bool(0))
        self.y = Signal(bool(0))

def mod_with_interface(intf):
    global me
    xi = me
    @always(intf.clock.posedge)
    def rtl():
        intf.y.next = (x + xi) & 1
    me += 1
    return rtl
    
def list_of_interfaces_top(clock, x, y, number_of_modules=120):
    loi = [Interface() for _ in range(number_of_modules)]
    mods = []
    for ii, intf in enumerate(loi):
        if ii == 0:
            intf.x = x
        elif ii == number_of_modules-1:
            intf.y = y
        else:
            intf.x = loi[ii-1].x
        intf.clock = clock
        mods += [mod_with_interface(intf)]
    return mods
        
clock = Signal(bool(0))
x, y = [Signal(bool(0)) for _ in range(2)]
toVerilog(list_of_interfaces_top, clock, x, y)