Commits

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Author Commit Message Labels Comments Date
Evan Cheng
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
Tags
2 tags
Evan Cheng
Rewrite address mode 1 code emission routines.
Duncan Sands
The "alias" keyword comes first.
Evan Cheng
On some targets, non-move instructions can become move instructions because of coalescing. e.g. vr2 = OR vr0, vr1 => vr2 = OR vr1, vr1 // after coalescing vr0 with vr1 Update the value# of the destination register with the copy instruction if that happens.
Dan Gohman
Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and ConstantFP* instead of APInt and APFloat directly. This reduces the amount of time to create ConstantSDNode and ConstantFPSDNode nodes when ConstantInt* and ConstantFP* respectively are already available, as is the case in SelectionDAGBuild.cpp. Also, it reduces the amount of time to legalize constants into constant pools, and the amount of time to add ConstantFP operands to MachineInstrs, due to eliminating ConstantInt::get and ConstantFP::get ca…
Dale Johannesen
Pass "earlyclobber" bit through to machine representation; coalescer and RA need to know about it. No functional change.
Dan Gohman
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue.
Duncan Sands
Give GlobalsModRef a whirl in the nightly testers. I placed it just before GVN because that it is the pass most likely to benefit from it. Some quick and dirty testing confirms that this is a decent place for it.
Duncan Sands
Rather than marking all internal globals "Ref" when a readonly declaration is called, set a flag. This is faster and uses less memory. In theory it is less accurate, because before only those internal globals that were read by someone were being marked "Ref", but now all are. But in practice, thanks to other passes, all internal globals of the kind considered here will be both read and stored to: those only read will have been turned into co…
Dale Johannesen
The sequence for ppcf128 compares was not IEEE safe in the presence of NaNs.
Tags
checker-90
Dan Gohman
On 64-bit targets, change 32-bit getelementptr indices to be 64-bit getelementptr indices, inserting an explicit cast if necessary. This helps expose the sign-extension operation to other optimizations.
Dan Gohman
Fix a vectorshuffle instcombine bug introduced by r55995. Patch by Nicolas Capens!
Arnold Schwaighofer
Add indirect tail call (function pointer) examples.
Jim Grosbach
udpate header comment: s/VP/VFP/
Arnold Schwaighofer
When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.
Tags
checker/checker-90
Evan Cheng
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g. vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.
Owen Anderson
Fix a bug in ANY_EXTEND handling that was breaking 403.gcc on X86-64 in fast isel.
Duncan Sands
Fix comment typo.
Duncan Sands
Intrinsics don't touch internal global variables (unless passed one via a parameter), even if they are IntrWriteMem.
Dan Gohman
Fix a copy+paste bug that Duncan spotted. For several cases it was still getting lucky and detecting overflow but it was clearly incorrect.
Evan Cheng
Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.
Evan Cheng
Eliminate some unused methods.
Evan Cheng
Indentation.
Jim Grosbach
lib/Target/SubtargetFeature.cpp asserts that the FeatureKV[] table be sorted by its first field, but TableGen doesn't actually enforce creating it that way. TableGen sorts the records that will be used to create it by the names of the records, not the Name field of those records. This patch corrects the sort to use the "Name" field of the record as the sort key.
Duncan Sands
Intrinsics don't read these kinds of global variables.
Evan Cheng
Change getSubReg semantics. It now returns zero if the specified register doesn't have a subreg of the specified index.
Evan Cheng
Fix a 80 column violation.
Dale Johannesen
The version of AtomicSDNode::AtomicSDNode used (only) for cmp-and-swap reversed the Cmp and Swap arguments; comments make it clear this is unintentional. Unfortunately, the x86 BE had a compensating reversal, which is removed here. PPC is OK. From inspection of the Alpha code I think it is OK, but if somebody has that platform please check it out. I cannot test on that platform.
Owen Anderson
If ISD::ANY_EXTEND fails, try ISD::ZERO_EXTEND and ISD::SIGN_EXTEND before giving up. This fixes 445.gobmk on X86-64 in fast isel.
Dale Johannesen
Succumb utterly to compatibility and implement __sync_fetch_and_nand as ANDC, even though that's not what nand means.
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