Commits

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Author Commit Message Labels Comments Date
Dale Johannesen
Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis and redo as linked list walk. Logic moved into RA. Per review feedback.
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Devang Patel
splitLoop does not handle split condition EQ. Fixes PR 2805
Dan Gohman
Address-mode folding for X86FastISel. It's pretty basic, but it catches a fair number of common cases. Note that this currently causes Fast-ISel to leave behind lots of dead instructions. Those will be dealt with in subsequent commits.
Bill Wendling
Decrementing the iterator here could be wrong if the worklist is empty after the "erase". Thanks to Ji Young Park for the patch!
Devang Patel
Try to place hoisted instructions befoe icmp instruction.
Evan Cheng
Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
Dan Gohman
Simplify this code. The FastISel class has its own TD member.
Dan Gohman
Don't consider instructions with implicit physical register defs to be necessarily live.
Tanya Lattner (Tanya Brethour)
Upgrade doxygen.
Dan Gohman
Add a new "fast" scheduler. This is currently basically just a copy of the BURRList scheduler, but with several parts ripped out, such as backtracking, online topological sort maintenance (needed by backtracking), the priority queue, and Sethi-Ullman number computation and maintenance (needed by the priority queue). As a result of all this, it generates somewhat lower quality code, but that's its tradeoff for running about 30% faster than list-burr in -fast mode in many cases. This is somewhat experimental. Moving forward, major pieces of this can be refactored with pieces in common with ScheduleDAGRRList.cpp.
Evan Cheng
Preliminary support for systems which require changing JIT memory regions privilege from read / write to read / executable.
Evan Cheng
Duh. Default to ARMCC::AL (always).
Evan Cheng
Clean up.
Evan Cheng
Cosmetic.
Dan Gohman
FastISel: For calls, prefer using the callee's address as a constant over having it in a register. And wait until after checking type legality before requesting that the callee address be placed in a register. Also, fix support for calls with void return type. This speeds up fast-isel isel time by about 15% and reduces instruction counts by about 3% overall on certain testcases. It also changes many indirect calls to direct calls.
Dale Johannesen
Add a bit to mark operands of asm's that conflict with an earlyclobber operand elsewhere. Propagate this bit and the earlyclobber bit through SDISel. Change linear-scan RA not to allocate regs in a way that conflicts with an earlyclobber. See also comments.
Evan Cheng
Unallocatable registers do not have live intervals.
Devang Patel
Do not hoist instruction above branch condition. The instruction may use branch condition.
Devang Patel
Do not ignore iv uses outside the loop. This one slipped through cracks very well.
Devang Patel
Fix comments, help messages.
Dan Gohman
Don't worry about clobbering physical register defs that aren't used.
Evan Cheng
Fix addrmode1 instruction encodings; fix bx_ret encoding.
Evan Cheng
Specify instruction encoding using range list to avoid endianess issues.
Evan Cheng
Add instruction names as comments to InstBits entries.
Dan Gohman
Simplify and generalize X86DAGToDAGISel::CanBeFoldedBy, and draw up some new ascii art to illustrate what it does. This change currently has no effect on generated code.
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Dan Gohman
Add a new MachineInstr-level DCE pass. It is very simple, and is intended to be used with fast-isel.
Bill Wendling
Add trampoline support to PPC. GCC simply calls the "__trampoline_setup" function with appropriate parameters. This allows us to support blocks on PPC.
Devang Patel
Fix cut-n-pasto.
Evan Cheng
When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
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2 tags
Devang Patel
Remove.
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