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Gabor Greif
Provide two overloads of AnalyzeNewNode. The first can update the SDNode in an SDValue while the second is called with SDNode* and returns a possibly updated SDNode*. This patch has no intended functional impact, but helps eliminating ugly temporary SDValues.
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Duncan Sands
Even though no caller actually uses the new value (what matters is that it is added to the worklist), it seems more logical to return it.
Duncan Sands
Turn this legalize types test on.
Duncan Sands
Add a small pass that sets the readnone/readonly attributes on functions, based on the result of alias analysis. It's not hardwired to use GlobalsModRef even though this is the only (AFAIK) alias analysis that results in this pass actually doing something. Enable as follows: opt ... -globalsmodref-aa -markmodref ... Advantages of this pass: (1) records the result of globalsmodref in the bitcode, meaning it is available for use by later passe…
Evan Cheng
Control flow instruction encodings.
Evan Cheng
ldm / stm instruction encodings.
Evan Cheng
AXI2 and AXI3 instruction encodings.
Evan Cheng
Reorganize instruction formats again; AXI1 encoding.
Evan Cheng
addrmode3 instruction encodings.
Evan Cheng
Reorganize some instruction format definitions. No functionality change.
Evan Cheng
Rest of addrmode2 instruction encodings.
Evan Cheng
Addr2 word / byte load encodings.
Evan Cheng
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
Gabor Greif
fix a bunch of 80-col violations
Bill Wendling
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR instructions in CellSPU as "Expand" so that they won't be generated. I added a "FIXME" so that this hack can be addressed and reverted once ISD::ROTR is supported in the .td files.
Bill Wendling
Expand for ROTR with MVT::i64. Dale, Could you please review this?
Bill Wendling
CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG combiner can now generate ROTR if the backend says that it can handle it. Cell SPU says this, but gets an error from code gen saying that it can't select ROTR. I'm xfailing this test until this can be fixed.
Bill Wendling
Cosmetic changes to Machine LICM. No functionality change.
Bill Wendling
Another situation where ROTR is cheaper than ROTL.
Bill Wendling
For this pattern, ROTR is the cheaper option.
Bill Wendling
- Fix comment so that it describes how the code really works: // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> // (rotl x, y) // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> // (rotr x, (sub 32, y)) Example: (x == 0xDEADBEEF and y == 4) (x << 4) | (x >> 28) => 0xEADBEEF0 | 0x0000000D => 0xEADBEEFD (rotl x, 4) => 0xEADBEEFD (rotr x, 28) => 0xEADBEEFD - Fix comment and code for second version. I…
Gabor Greif
typo
Gabor Greif
fix some 80-col violations
Gordon Henriksen
PR2731: C and Ocaml bindings for setTailCall and isTailCall. Based on patch by Giorgos Korfiatis.
Gordon Henriksen
Fix ConstantExpr::getInsertElement. Breakage was exposed in the Ocaml bindings tests after Chris uncommented an assertion in r55084.
Gabor Greif
fix some 80-col violations
Evan Cheng
Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.
Evan Cheng
Fold isRematerializable checks into isSafeToReMat.
Evan Cheng
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
Evan Cheng
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
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