Commits

Dan Strother committed 0e11ec8

added COUNT/FREE parameters to make use of rd_count/wr_free explicit

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Files changed (3)

mem/rtl/dlsc_fifo.v

         .ADDR           ( ADDR ),
         .ALMOST_FULL    ( ALMOST_FULL ),
         .ALMOST_EMPTY   ( ALMOST_EMPTY ),
+        .COUNT          ( COUNT ),
+        .FREE           ( FREE ),
         .FAST_FLAGS     ( FAST_FLAGS ),
         .FULL_IN_RESET  ( FULL_IN_RESET ),
         .BRAM           ( BRAM )

mem/rtl/dlsc_fifo_counter.v

 
 parameter ALMOST_FULL   = 0;                    // assert almost_full when <= ALMOST_FULL free spaces remain
 parameter ALMOST_EMPTY  = 0;                    // assert almost_empty when <= ALMOST_EMPTY valid entries remain
-parameter FAST_FLAGS    = 0;                    // disallow pessimistic flags
+parameter COUNT         = 0;                    // enable rd_count port
+parameter FREE          = 0;                    // enable wr_free port
+parameter FAST_FLAGS    = 1;                    // disallow pessimistic flags
 parameter FULL_IN_RESET = 0;                    // force full flags to be set when in reset
 
 
 
 // input
 input   wire                wr_push;
-output  wire                wr_full;
+output  reg                 wr_full;
 output  wire                wr_almost_full;
 output  wire    [ADDR:0]    wr_free;
 
 // output
 input   wire                rd_pop;
-output  wire                rd_empty;
+output  reg                 rd_empty;
 output  wire                rd_almost_empty;
 output  wire    [ADDR:0]    rd_count;
 
 // ** Flags **
 
 reg  [ADDR:0]   cnt;        // 1 extra bit, since we want to store [0,DEPTHI] (not just DEPTHI-1)
+reg  [ADDR:0]   free;
 reg             almost_empty;
 reg             almost_full;
 reg             rst_done;
 assign          rd_almost_empty = (ALMOST_EMPTY==0) ? rd_empty : almost_empty;
 assign          wr_almost_full  = (ALMOST_FULL ==0) ? wr_full  : almost_full;
 
-assign          rd_count        = cnt;
+assign          rd_count        = COUNT ? cnt  : {(ADDR+1){1'bx}};
+assign          wr_free         = FREE  ? free : {(ADDR+1){1'bx}};
 
 wire            inc             =  wr_push && !rd_pop;
 wire            dec             = !wr_push &&  rd_pop;
     if(rst) begin
         // counts
         cnt             <= 0;
-        wr_free         <= DEPTHI;
+        free            <= DEPTHI;
         // empty flags
         rd_empty        <= 1'b1;
         almost_empty    <= 1'b1;
         // pushed; count increments
         if(inc) begin
             cnt             <= cnt + 1;
-            wr_free         <= wr_free - 1;
+            free            <= free - 1;
             wr_full         <= (cnt == (DEPTHI-1)); // cnt will be DEPTHI (full)
             if(cnt == (       ALMOST_EMPTY  )) almost_empty <= 1'b0;
             if(cnt == (DEPTHI-ALMOST_FULL -1)) almost_full  <= 1'b1;
         // popped; count decrements
         if(dec) begin
             cnt             <= cnt - 1;
-            wr_free         <= wr_free + 1;
+            free            <= free + 1;
             wr_full         <= 1'b0;                // can't be full on pop
             if(cnt == (       ALMOST_EMPTY+1)) almost_empty <= 1'b1;
             if(cnt == (DEPTHI-ALMOST_FULL   )) almost_full  <= 1'b0;

mem/rtl/dlsc_fifo_ram.v

     parameter ADDR          = 4,    // depth of FIFO is 2**ADDR
     parameter ALMOST_FULL   = 0,    // assert almost_full when <= ALMOST_FULL free spaces remain (0 makes it equivalent to full)
     parameter ALMOST_EMPTY  = 0,    // assert almost_empty when <= ALMOST_EMPTY valid entries remain (0 makes it equivalent to empty)
+    parameter COUNT         = 0,    // enable rd_count port
+    parameter FREE          = 0,    // enable wr_free port
     parameter FAST_FLAGS    = 0,    // disallow pessimistic flags
     parameter FULL_IN_RESET = 0,    // force full flags to be set when in reset
     parameter BRAM          = (DATA*(2**ADDR)>=4096) // use block RAM (instead of distributed RAM)
 
 // ** flags **
 
+wire [ADDR:0]   cnt;
+wire [ADDR:0]   free;
+
+assign          rd_count        = COUNT ? cnt  : {(ADDR+1){1'bx}};
+assign          wr_free         = FREE  ? free : {(ADDR+1){1'bx}};
+
 dlsc_fifo_counter #(
     .ADDR           ( ADDR ),
     .ALMOST_FULL    ( ALMOST_FULL ),
     .ALMOST_EMPTY   ( ALMOST_EMPTY ),
+    .COUNT          ( 1 ),              // we need rd_count to generate rd_en
+    .FREE           ( FREE ),
     .FAST_FLAGS     ( FAST_FLAGS ),
     .FULL_IN_RESET  ( FULL_IN_RESET )
 ) dlsc_fifo_counter_inst (
     .wr_push        ( wr_push ),
     .wr_full        ( wr_full ),
     .wr_almost_full ( wr_almost_full ),
-    .wr_free        ( wr_free ),
+    .wr_free        ( free ),
     .rd_pop         ( rd_pop ),
     .rd_empty       ( rd_empty ),
     .rd_almost_empty( rd_almost_empty ),
-    .rd_count       ( rd_count )
+    .rd_count       ( cnt )
 );
 
 // read on pop, or after first entry is written
-assign          rd_en           = rd_pop || (rd_empty && rd_count == 1);
+assign          rd_en           = rd_pop || (rd_empty && cnt == 1);
 
 endmodule