Commits

Author Commit Message Labels Comments Date
Dan Strother
modified to use typedef for sockets, in order to support multi-initiator
Dan Strother
fixed crash on reset due to problematic iterator usage
Dan Strother
removed unsupported usage of dlsc_warn in non-sc_module
Dan Strother
separated AXI RTL and AXI TLM stuff
Dan Strother
simplified fifo_shiftreg empty flag behavior
Dan Strother
updated file lists
Dan Strother
improved rstsync module to support multiple output clock domains
Dan Strother
created domaincross_rvh testbench; fixed handshaking bug; improved reset handling
Dan Strother
created ready/valid-handshake version of domaincross
Dan Strother
changed initialization value to match reset value
Dan Strother
optimized async FIFO for maximum clock frequency (at a slight cost of additional latency)
Dan Strother
created async FIFO
Dan Strother
added gray-code <-> binary converters
Dan Strother
created uart rx/tx wrapper
Dan Strother
simplified uart receiver
Dan Strother
simplified uart transmitter
Dan Strother
added uart transmitter core
Dan Strother
added rx_mask input to uart (e.g. for temporarily disabling reception in a half-duplex system)
Dan Strother
modified enable generation to reduce activity when idle
Dan Strother
created uart receiver core
Dan Strother
created glitch filter
Dan Strother
initial version of VNG demosaic core logic
Dan Strother
modified reset fanout control (split delay line into individual registers with separate fanout control directives.. XST seemed to only apply the fanout directive to the last one when declared as a single multi-bit register)
Dan Strother
added test for non-power-of-2 MULT_D
Dan Strother
added VCD target (in addition to existing LXT2 waves target), and modified to have a results summary printed after a sims run
Dan Strother
added top-level readme with copyright/license information
Dan Strother
added global gen target
Dan Strother
added test of mid-frame reset
Dan Strother
created plain Verilog testbench for dlsc_stereobm
Dan Strother
moved scaling/cropping into common models file
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