David Lin avatar David Lin committed 49b959c

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Files changed (5)

project2/Makefile

 SOURCES := code/*.v
 
 CPU: $(SOURCES)
-	iverilog -I code -o $@ $^
+	iverilog -s TestBench -I code -o $@ $^
 
 clean:
 	rm -f CPU output.txt cache.txt

project2/code/CPU.v

   wire M_memread = EX_Buf_M.data_o[0];
   wire M_memwrite = EX_Buf_M.data_o[1];
   
+  wire [31:0] M_memdata_o;
+  
   wire M_Buf_write = !MEM_stall;
   
+`ifdef USE_CACHE
+  
   dcache_top dcache
   (
     // System clock, reset and stall
     .p1_addr_i(EX_Buf_ALUOut.data_o),
     .p1_MemRead_i(M_memread),
     .p1_MemWrite_i(M_memwrite),
-    .p1_data_o(),
+    .p1_data_o(M_memdata_o),
     .p1_stall_o(MEM_stall)
   );
   
-  /*
-  DataMemory DMem (
+`else
+  
+  DataMemory_dbg DMem (
     .clock_i(clock_i), 
     .addr_i(EX_Buf_ALUOut.data_o),
     .data_i(EX_Buf_RtData.data_o),
-    .read_i(M_memread), .write_i(M_memwrite)
+    .read_i(M_memread), .write_i(M_memwrite),
+    .data_o(M_memdata_o)
   );
-  */
+  
+  assign MEM_stall = 0;
+
+`endif
   
   // ALU Output Buffer
   Buffer #(.BITS(32)) M_Buf_ALUOut (
   // Memory Read Buffer
   Buffer #(.BITS(32)) M_Buf_MemData(
     .clock_i(clock_i), .reset_i(reset_i), .write_i(M_Buf_write), 
-    .data_i(dcache.p1_data_o), .clear_i(0)
+    .data_i(M_memdata_o), .clear_i(0)
   );
   
   // Control Buffers

project2/code/Defs.v

 `define ALUCTRL_AND    3'b010
 `define ALUCTRL_OR     3'b011
 `define ALUCTRL_MUL    3'b100
+
+//`define USE_CACHE
+

project2/code/Memory.v

   
 endmodule
 
+// Data Memory
+module DataMemory_dbg 
+( clock_i, addr_i, data_i, read_i, write_i, data_o );
+  
+  parameter ADDR_BITS = 32;
+  parameter WORD_BITS = 32;
+  parameter SIZE = 16384;
+  
+  input clock_i;
+  input [ADDR_BITS-1:0] addr_i;
+  input [WORD_BITS-1:0] data_i;
+  input read_i, write_i;
+  
+  output [WORD_BITS-1:0] data_o;
+  
+  // Memory
+  reg [7:0] _content [0:SIZE-1];
+  
+  // Write
+  always @ (posedge clock_i)
+  begin
+    if (write_i)
+    begin
+      _content[addr_i+3] <= data_i[31:24];
+      _content[addr_i+2] <= data_i[23:16];
+      _content[addr_i+1] <= data_i[15:8];
+      _content[addr_i  ] <= data_i[7:0];
+    end
+  end
+  
+  // Read
+  assign data_o = (read_i) ? { _content[addr_i+3], 
+                               _content[addr_i+2],
+                               _content[addr_i+1],
+                               _content[addr_i  ] }
+                           : 32'b0;
+  
+endmodule
+

project2/code/TestBench.v

+`include "Defs.v"
+
 `define CYCLE_TIME 50			
 
 module TestBench;
 	end
 	
 	// initialize data memory	(16KB)
+`ifdef USE_CACHE
 	for(i=0; i<512; i=i+1) begin
 		Data_Memory.memory[i] = 256'b0;
 	end
+`else
+	for (i=0; i<CPU.DMem.SIZE; i=i+1)
+    begin
+      CPU.DMem._content[i] = 0;
+    end
+`endif
 		
 	// initialize cache memory	(1KB)
+`ifdef USE_CACHE
 	for(i=0; i<32; i=i+1) begin
 		CPU.dcache.dcache_tag_sram.memory[i] = 24'b0;
 		CPU.dcache.dcache_data_sram.memory[i] = 256'b0;
 	end
+`endif
 	
 	// initialize Register File
 	for(i=0; i<CPU.RegFile.SIZE; i=i+1) begin
 end
   
 always@(posedge Clk) begin
+`ifdef USE_CACHE
 	if(counter == 150) begin	// store cache to memory
 		$fdisplay(outfile, "Flush Cache! \n");
 		for(i=0; i<32; i=i+1) begin
 			Data_Memory.memory[address] = CPU.dcache.dcache_data_sram.memory[i];
 		end 
 	end
+`endif
 	if(counter > 150) begin	// stop 
 		$finish;
 	end
               CPU.RegFile._content[23], CPU.RegFile._content[31]);
 
 	// print Data Memory
+`ifdef USE_CACHE
 	$fdisplay(outfile, "Data Memory: 0x0000 = %h", Data_Memory.memory[0]);
 	$fdisplay(outfile, "Data Memory: 0x0020 = %h", Data_Memory.memory[1]);
 	$fdisplay(outfile, "Data Memory: 0x0040 = %h", Data_Memory.memory[2]);
 	$fdisplay(outfile, "Data Memory: 0x00C0 = %h", Data_Memory.memory[6]);
 	$fdisplay(outfile, "Data Memory: 0x00E0 = %h", Data_Memory.memory[7]);
 	$fdisplay(outfile, "Data Memory: 0x0400 = %h", Data_Memory.memory[32]);
+`else
+    for(i = 0; i < 8 || i == 32; i=i+1)
+    begin
+      $fdisplay(outfile, "Data Memory: 0x%h = %h",  ( i * 16'd32 ), 
+                                                   {CPU.DMem._content[32*i+31] , 
+                                                    CPU.DMem._content[32*i+30] , 
+                                                    CPU.DMem._content[32*i+29] , 
+                                                    CPU.DMem._content[32*i+28] , 
+                                                    CPU.DMem._content[32*i+27] , 
+                                                    CPU.DMem._content[32*i+26] , 
+                                                    CPU.DMem._content[32*i+25] , 
+                                                    CPU.DMem._content[32*i+24] , 
+                                                    CPU.DMem._content[32*i+23] , 
+                                                    CPU.DMem._content[32*i+22] , 
+                                                    CPU.DMem._content[32*i+21] , 
+                                                    CPU.DMem._content[32*i+20] , 
+                                                    CPU.DMem._content[32*i+19] , 
+                                                    CPU.DMem._content[32*i+18] , 
+                                                    CPU.DMem._content[32*i+17] , 
+                                                    CPU.DMem._content[32*i+16] , 
+                                                    CPU.DMem._content[32*i+15] , 
+                                                    CPU.DMem._content[32*i+14] , 
+                                                    CPU.DMem._content[32*i+13] , 
+                                                    CPU.DMem._content[32*i+12] , 
+                                                    CPU.DMem._content[32*i+11] , 
+                                                    CPU.DMem._content[32*i+10] , 
+                                                    CPU.DMem._content[32*i+ 9] , 
+                                                    CPU.DMem._content[32*i+ 8] , 
+                                                    CPU.DMem._content[32*i+ 7] , 
+                                                    CPU.DMem._content[32*i+ 6] , 
+                                                    CPU.DMem._content[32*i+ 5] , 
+                                                    CPU.DMem._content[32*i+ 4] , 
+                                                    CPU.DMem._content[32*i+ 3] , 
+                                                    CPU.DMem._content[32*i+ 2] , 
+                                                    CPU.DMem._content[32*i+ 1] , 
+                                                    CPU.DMem._content[32*i+ 0]
+                                                   });
+      if (i == 7)
+        i = 31;
+    end
+`endif
 	
 	$fdisplay(outfile, "\n");
 	
 	// print Data Cache Status
+`ifdef USE_CACHE
 	if(CPU.dcache.p1_stall_o && CPU.dcache.state==0) begin
 		if(CPU.dcache.sram_dirty) begin
 			if(CPU.dcache.p1_MemWrite_i) 
 		end
 		flag = 1'b0;
 	end
-		
+`endif
 	
 	counter = counter + 1;
 end
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