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David Lin committed d615127

Start Debugging Cache

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  • Parent commits 65139f6

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project2/code/CPU.v

   // Stage IF
   
   ProgramCounter PC (
-    .clock_i(clock_i), .reset_i(reset_i), .run_i(pc_run & !MEM_stall),
+    .clock_i(clock_i), .reset_i(reset_i), .run_i(pc_run & !MEM_stall), // TODO: debug
     .pc_i(pc_next),
     .pc_o()
   );
   );
   
   // 
-  wire IF_Buf_write = ID_Hazard.IF_ID_Write_o & !MEM_stall;
+  // TODO: debug
+  wire IF_Buf_write = pc_flush || (ID_Hazard.IF_ID_Write_o & !MEM_stall);
   wire IF_Buf_clear = pc_flush;
   
   // Instruction Buffer
   wire [25:0] ID_jmp_target = IF_Buf_Instruction.data_o[25:0];
   wire [31:0] ID_rs_data, ID_rt_data;
   
-  wire ID_Buf_write = !MEM_stall;
+  // TODO: debug
+  wire ID_Buf_write = !control_propagation || !MEM_stall;
+  wire ID_Buf_clear = !control_propagation;
   
   // Control
   Control ID_Ctrl( .opcode_i(ID_opcode) );
   // Control Buffers
   Buffer #(.BITS(4)) ID_Buf_EX ( 
     .clock_i(clock_i), .reset_i(reset_i), .write_i(ID_Buf_write), 
-    .data_i(ID_Ctrl.ctrl_EX_o), .clear_i(!control_propagation)
+    .data_i(ID_Ctrl.ctrl_EX_o), .clear_i(ID_Buf_clear)
   );
   Buffer #(.BITS(2)) ID_Buf_M  ( 
     .clock_i(clock_i), .reset_i(reset_i), .write_i(ID_Buf_write), 
-    .data_i(ID_Ctrl.ctrl_M_o), .clear_i(!control_propagation)
+    .data_i(ID_Ctrl.ctrl_M_o), .clear_i(ID_Buf_clear)
   );
   Buffer #(.BITS(2)) ID_Buf_WB ( 
     .clock_i(clock_i), .reset_i(reset_i), .write_i(ID_Buf_write), 
-    .data_i(ID_Ctrl.ctrl_WB_o), .clear_i(!control_propagation)
+    .data_i(ID_Ctrl.ctrl_WB_o), .clear_i(ID_Buf_clear)
   );
   
   // Register Buffers
   wire [5:0] EX_funct = ID_Buf_Immediate.data_o[5:0];
   wire [31:0] EX_dataA, EX_dataB;
   
+  // TODO: debug
   wire EX_Buf_write = !MEM_stall;
+  wire EX_Buf_clear = 0;
   
   // ALU-DataA-Src
   assign EX_dataA = EX_forwarded_rs_data;
   // Control Buffers
   Buffer #(.BITS(2)) EX_Buf_M  ( 
     .clock_i(clock_i), .reset_i(reset_i), .write_i(EX_Buf_write), 
-    .data_i(ID_Buf_M.data_o), .clear_i(0)
+    .data_i(ID_Buf_M.data_o), .clear_i(EX_Buf_clear)
   );
   Buffer #(.BITS(2)) EX_Buf_WB ( 
     .clock_i(clock_i), .reset_i(reset_i), .write_i(EX_Buf_write), 
-    .data_i(ID_Buf_WB.data_o), .clear_i(0)
+    .data_i(ID_Buf_WB.data_o), .clear_i(EX_Buf_clear)
   );
   
   // Rt Data Buffer
   
   wire [31:0] M_memdata_o;
   
+  // TODO: debug
   wire M_Buf_write = !MEM_stall;
+  wire M_Buf_clear = 0;
   
 `ifdef USE_CACHE
   
     .p1_stall_o()
   );
   
-  assign MEM_stall = 0; //dcache.p1_stall_o;
+  assign MEM_stall = dcache.p1_stall_o; // TODO: debug
   
 `else
   
   // Control Buffers
   Buffer #(.BITS(2)) M_Buf_WB ( 
     .clock_i(clock_i), .reset_i(reset_i), .write_i(M_Buf_write), 
-    .data_i(EX_Buf_WB.data_o), .clear_i(0)
+    .data_i(EX_Buf_WB.data_o), .clear_i(M_Buf_clear)
   );
   
   // ==============================================================================

project2/code/TestBench.v

 
 always #(`CYCLE_TIME/2) Clk = ~Clk;	
 
-CPU CPU(
+CPU cpu(
 	.clock_i  (Clk),
     .reset_i  (!Reset),
 	.start_i  (Start),
 	counter = 1;
 	
 	// initialize instruction memory (2KB)
-	for(i=0; i<CPU.IMem.SIZE; i=i+1) begin
-		CPU.IMem._content[i] = 32'b0;
+	for(i=0; i<cpu.IMem.SIZE; i=i+1) begin
+		cpu.IMem._content[i] = 32'b0;
 	end
 	
 	// initialize data memory	(16KB)
 		Data_Memory.memory[i] = 256'b0;
 	end
 `else
-	for (i=0; i<CPU.DMem.SIZE; i=i+1)
+	for (i=0; i<cpu.DMem.SIZE; i=i+1)
     begin
-      CPU.DMem._content[i] = 0;
+      cpu.DMem._content[i] = 0;
     end
 `endif
 		
 	// initialize cache memory	(1KB)
 `ifdef USE_CACHE
 	for(i=0; i<32; i=i+1) begin
-		CPU.dcache.dcache_tag_sram.memory[i] = 24'b0;
-		CPU.dcache.dcache_data_sram.memory[i] = 256'b0;
+		cpu.dcache.dcache_tag_sram.memory[i] = 24'b0;
+		cpu.dcache.dcache_data_sram.memory[i] = 256'b0;
 	end
 `else
 `endif
 	
 	// initialize Register File
-	for(i=0; i<CPU.RegFile.SIZE; i=i+1) begin
-		CPU.RegFile._content[i] = 32'b0;
+	for(i=0; i<cpu.RegFile.SIZE; i=i+1) begin
+		cpu.RegFile._content[i] = 32'b0;
 	end
 	
 	// Load instructions into instruction memory
-	$readmemb("instruction.txt", CPU.IMem._content);
+	$readmemb("instruction.txt", cpu.IMem._content);
 	
 	// Open output file
 	outfile = $fopen("output.txt") | 1;
 `ifdef USE_CACHE
 	Data_Memory.memory[0] = 256'h5;		// n = 5 for example
 `else
-	CPU.DMem._content[0] = 8'h5;
+	cpu.DMem._content[0] = 8'h5;
 `endif
 	
     Clk = 0;
 	if(counter == 150) begin	// store cache to memory
 		$fdisplay(outfile, "Flush Cache! \n");
 		for(i=0; i<32; i=i+1) begin
-			tag = CPU.dcache.dcache_tag_sram.memory[i];
+			tag = cpu.dcache.dcache_tag_sram.memory[i];
 			index = i;
 			address = {tag[21:0], index};
-			Data_Memory.memory[address] = CPU.dcache.dcache_data_sram.memory[i];
+			Data_Memory.memory[address] = cpu.dcache.dcache_data_sram.memory[i];
 		end 
 	end
 `endif
 		
 	$fdisplay(outfile, "cycle = %d, Start = %b", counter, Start);
 	// print PC 
-	$fdisplay(outfile, "PC = %d", CPU.PC.pc_o);
+	$fdisplay(outfile, "PC = %d", cpu.PC.pc_o);
 	
 	// print Registers
 	$fdisplay(outfile, "Registers");
     $fdisplay(outfile, "R0(r0) = %h, R8 (t0) = %h, R16(s0) = %h, R24(t8) = %h", 
-              CPU.RegFile._content[0], CPU.RegFile._content[8] , 
-              CPU.RegFile._content[16], CPU.RegFile._content[24]);
+              cpu.RegFile._content[0], cpu.RegFile._content[8] , 
+              cpu.RegFile._content[16], cpu.RegFile._content[24]);
     $fdisplay(outfile, "R1(at) = %h, R9 (t1) = %h, R17(s1) = %h, R25(t9) = %h", 
-              CPU.RegFile._content[1], CPU.RegFile._content[9] , 
-              CPU.RegFile._content[17], CPU.RegFile._content[25]);
+              cpu.RegFile._content[1], cpu.RegFile._content[9] , 
+              cpu.RegFile._content[17], cpu.RegFile._content[25]);
     $fdisplay(outfile, "R2(v0) = %h, R10(t2) = %h, R18(s2) = %h, R26(k0) = %h", 
-              CPU.RegFile._content[2], CPU.RegFile._content[10], 
-              CPU.RegFile._content[18], CPU.RegFile._content[26]);
+              cpu.RegFile._content[2], cpu.RegFile._content[10], 
+              cpu.RegFile._content[18], cpu.RegFile._content[26]);
     $fdisplay(outfile, "R3(v1) = %h, R11(t3) = %h, R19(s3) = %h, R27(k1) = %h", 
-              CPU.RegFile._content[3], CPU.RegFile._content[11], 
-              CPU.RegFile._content[19], CPU.RegFile._content[27]);
+              cpu.RegFile._content[3], cpu.RegFile._content[11], 
+              cpu.RegFile._content[19], cpu.RegFile._content[27]);
     $fdisplay(outfile, "R4(a0) = %h, R12(t4) = %h, R20(s4) = %h, R28(gp) = %h", 
-              CPU.RegFile._content[4], CPU.RegFile._content[12], 
-              CPU.RegFile._content[20], CPU.RegFile._content[28]);
+              cpu.RegFile._content[4], cpu.RegFile._content[12], 
+              cpu.RegFile._content[20], cpu.RegFile._content[28]);
     $fdisplay(outfile, "R5(a1) = %h, R13(t5) = %h, R21(s5) = %h, R29(sp) = %h", 
-              CPU.RegFile._content[5], CPU.RegFile._content[13], 
-              CPU.RegFile._content[21], CPU.RegFile._content[29]);
+              cpu.RegFile._content[5], cpu.RegFile._content[13], 
+              cpu.RegFile._content[21], cpu.RegFile._content[29]);
     $fdisplay(outfile, "R6(a2) = %h, R14(t6) = %h, R22(s6) = %h, R30(s8) = %h", 
-              CPU.RegFile._content[6], CPU.RegFile._content[14], 
-              CPU.RegFile._content[22], CPU.RegFile._content[30]);
+              cpu.RegFile._content[6], cpu.RegFile._content[14], 
+              cpu.RegFile._content[22], cpu.RegFile._content[30]);
     $fdisplay(outfile, "R7(a3) = %h, R15(t7) = %h, R23(s7) = %h, R31(ra) = %h", 
-              CPU.RegFile._content[7], CPU.RegFile._content[15], 
-              CPU.RegFile._content[23], CPU.RegFile._content[31]);
+              cpu.RegFile._content[7], cpu.RegFile._content[15], 
+              cpu.RegFile._content[23], cpu.RegFile._content[31]);
 
 	// print Data Memory
 `ifdef USE_CACHE
     for(i = 0; i < 8 || i == 32; i=i+1)
     begin
       $fdisplay(outfile, "Data Memory: 0x%h = %h",  ( i * 16'd32 ), 
-                                                   {CPU.DMem._content[32*i+31] , 
-                                                    CPU.DMem._content[32*i+30] , 
-                                                    CPU.DMem._content[32*i+29] , 
-                                                    CPU.DMem._content[32*i+28] , 
-                                                    CPU.DMem._content[32*i+27] , 
-                                                    CPU.DMem._content[32*i+26] , 
-                                                    CPU.DMem._content[32*i+25] , 
-                                                    CPU.DMem._content[32*i+24] , 
-                                                    CPU.DMem._content[32*i+23] , 
-                                                    CPU.DMem._content[32*i+22] , 
-                                                    CPU.DMem._content[32*i+21] , 
-                                                    CPU.DMem._content[32*i+20] , 
-                                                    CPU.DMem._content[32*i+19] , 
-                                                    CPU.DMem._content[32*i+18] , 
-                                                    CPU.DMem._content[32*i+17] , 
-                                                    CPU.DMem._content[32*i+16] , 
-                                                    CPU.DMem._content[32*i+15] , 
-                                                    CPU.DMem._content[32*i+14] , 
-                                                    CPU.DMem._content[32*i+13] , 
-                                                    CPU.DMem._content[32*i+12] , 
-                                                    CPU.DMem._content[32*i+11] , 
-                                                    CPU.DMem._content[32*i+10] , 
-                                                    CPU.DMem._content[32*i+ 9] , 
-                                                    CPU.DMem._content[32*i+ 8] , 
-                                                    CPU.DMem._content[32*i+ 7] , 
-                                                    CPU.DMem._content[32*i+ 6] , 
-                                                    CPU.DMem._content[32*i+ 5] , 
-                                                    CPU.DMem._content[32*i+ 4] , 
-                                                    CPU.DMem._content[32*i+ 3] , 
-                                                    CPU.DMem._content[32*i+ 2] , 
-                                                    CPU.DMem._content[32*i+ 1] , 
-                                                    CPU.DMem._content[32*i+ 0]
+                                                   {cpu.DMem._content[32*i+31] , 
+                                                    cpu.DMem._content[32*i+30] , 
+                                                    cpu.DMem._content[32*i+29] , 
+                                                    cpu.DMem._content[32*i+28] , 
+                                                    cpu.DMem._content[32*i+27] , 
+                                                    cpu.DMem._content[32*i+26] , 
+                                                    cpu.DMem._content[32*i+25] , 
+                                                    cpu.DMem._content[32*i+24] , 
+                                                    cpu.DMem._content[32*i+23] , 
+                                                    cpu.DMem._content[32*i+22] , 
+                                                    cpu.DMem._content[32*i+21] , 
+                                                    cpu.DMem._content[32*i+20] , 
+                                                    cpu.DMem._content[32*i+19] , 
+                                                    cpu.DMem._content[32*i+18] , 
+                                                    cpu.DMem._content[32*i+17] , 
+                                                    cpu.DMem._content[32*i+16] , 
+                                                    cpu.DMem._content[32*i+15] , 
+                                                    cpu.DMem._content[32*i+14] , 
+                                                    cpu.DMem._content[32*i+13] , 
+                                                    cpu.DMem._content[32*i+12] , 
+                                                    cpu.DMem._content[32*i+11] , 
+                                                    cpu.DMem._content[32*i+10] , 
+                                                    cpu.DMem._content[32*i+ 9] , 
+                                                    cpu.DMem._content[32*i+ 8] , 
+                                                    cpu.DMem._content[32*i+ 7] , 
+                                                    cpu.DMem._content[32*i+ 6] , 
+                                                    cpu.DMem._content[32*i+ 5] , 
+                                                    cpu.DMem._content[32*i+ 4] , 
+                                                    cpu.DMem._content[32*i+ 3] , 
+                                                    cpu.DMem._content[32*i+ 2] , 
+                                                    cpu.DMem._content[32*i+ 1] , 
+                                                    cpu.DMem._content[32*i+ 0]
                                                    });
       if (i == 7)
         i = 31;
     end
 `endif
 	
+	if (1) // Debug
+	begin
+	  $display("MEM_stall = %d\n", cpu.MEM_stall);
+	end
+	
 	$fdisplay(outfile, "\n");
 	
 	// print Data Cache Status
 `ifdef USE_CACHE
-	if(CPU.dcache.p1_stall_o && CPU.dcache.state==0) begin
-		if(CPU.dcache.sram_dirty) begin
-			if(CPU.dcache.p1_MemWrite_i) 
-				$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h (Write Back!)", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
-			else if(CPU.dcache.p1_MemRead_i) 
-				$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h (Write Back!)", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
+	if(cpu.dcache.p1_stall_o && cpu.dcache.state==0) begin
+		if(cpu.dcache.sram_dirty) begin
+			if(cpu.dcache.p1_MemWrite_i) 
+				$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h (Write Back!)", counter, cpu.dcache.p1_addr_i, cpu.dcache.p1_data_i);
+			else if(cpu.dcache.p1_MemRead_i) 
+				$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h (Write Back!)", counter, cpu.dcache.p1_addr_i, cpu.dcache.p1_data_o);
 		end
 		else begin
-			if(CPU.dcache.p1_MemWrite_i) 
-				$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
-			else if(CPU.dcache.p1_MemRead_i) 
-				$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
+			if(cpu.dcache.p1_MemWrite_i) 
+				$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h", counter, cpu.dcache.p1_addr_i, cpu.dcache.p1_data_i);
+			else if(cpu.dcache.p1_MemRead_i) 
+				$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h", counter, cpu.dcache.p1_addr_i, cpu.dcache.p1_data_o);
 		end
 		flag = 1'b1;
 	end
-	else if(!CPU.dcache.p1_stall_o) begin
+	else if(!cpu.dcache.p1_stall_o) begin
 		if(!flag) begin
-			if(CPU.dcache.p1_MemWrite_i) 
-				$fdisplay(outfile2, "Cycle: %d, Write Hit , Address: %h, Write Data: %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
-			else if(CPU.dcache.p1_MemRead_i) 
-				$fdisplay(outfile2, "Cycle: %d, Read Hit  , Address: %h, Read Data : %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
+			if(cpu.dcache.p1_MemWrite_i) 
+				$fdisplay(outfile2, "Cycle: %d, Write Hit , Address: %h, Write Data: %h", counter, cpu.dcache.p1_addr_i, cpu.dcache.p1_data_i);
+			else if(cpu.dcache.p1_MemRead_i) 
+				$fdisplay(outfile2, "Cycle: %d, Read Hit  , Address: %h, Read Data : %h", counter, cpu.dcache.p1_addr_i, cpu.dcache.p1_data_o);
 		end
 		flag = 1'b0;
 	end