Commits

Jordan Earls committed e694791

Removed Port0 crap
Added increment instruction
Changed the test bootrom to a simple program to continuously increment r0

Comments (0)

Files changed (9)

 def mov_reg_reg(reg1, reg2)
   do_group_reg_reg(5,1,reg1,reg2)
 end
+def inc_reg(reg1)
+  do_subgroup_reg(5,0,2,reg1);
+end
 
   
 
     raise "No suitable cmpneq opcode found";
   end
 end
+def inc(arg1)
+  if arg1.kind_of? Register8 then
+    inc_reg arg1
+  else
+    raise "No suitable inc opcode found";
+  end
+end
 
 def Label
   attr_accessor :name, :pos
 
 #port0(0) is LED port0(1) is a button
 
-mov r4, 1
-mov r5, 0xFD
-#mov r5, 0x01 #the port bitmask
-mov [r4],r5
-mov r3, 0
-mov [r3], 0
-mov r2, 0x02
-#poll for button
+
 new_label :loop
-mov r0, [r3]
-and_ r0, r2 #isolate just the button at pin 2
-cmpneq r0, 0
-if_tr_set{
-  mov [r3], 0x01
-}
-cmpeq r0,0
-if_tr_set{
-  mov [r3], 0x00
-}
+inc r0
 mov ip, lbl(:loop)
 
 printf("\n");

docs/design.md.txt

   RRR choices:
   000: push reg
   001: pop reg
+  010: increment reg
 001: mov reg, reg
 010: mov reg, [reg]
 011: mov [reg], reg
 architecture syn of bootrom is
   constant ROMSIZE: integer := 64;
   type ROM_TYPE is array(0 to ROMSIZE/2-1) of std_logic_vector(15 downto 0);
-  signal ROM: ROM_TYPE := (x"0801", x"0afd", x"5853", x"0600", x"1600", x"0402", x"5032", x"4020", x"3007", x"1701", x"3006", x"1700", x"0e0c", 
-x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
+  signal ROM: ROM_TYPE := (x"5020", x"0e00", 
+x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
+
+
+
   signal rdata : std_logic_vector(15 downto 0);
 begin
 
     Execute,
     WaitForMemory,
     HoldMemory,
-    WaitForAlu -- wait for settling is needed when using the ALU
+    WaitForAlu, -- wait for settling is needed when using the ALU
+    WaitForJump
   );
   signal state: ProcessorState;
   signal HeldState: ProcessorState; --state the processor was in when HOLD was activated
   signal UsuallySS: std_logic_vector(3 downto 0);
   signal UsuallyDS: std_logic_vector(3 downto 0);
   signal AluRegOut: std_logic_vector(3 downto 0);
+
+  signal JumpAddress: std_logic_vector(7 downto 0);
 begin
   reg: registerfile port map(
     WriteEnable => regWE,
         --regWE <= (others => '0');
         fetchEN <= '1'; --already enabled, but anyway
         --regWE <= (others => '0');
-        IPAddend <= x"02";
+        IPAddend <= x"00";
         SPAddend <= x"00"; --no addend unless pushing or popping
         RegWE <= (others => '0');
         regIn(REGIP) <= IPCarryOut;
         FetchEN <= '1';
         IPAddend <= x"02";
         SPAddend <= x"00";
+      elsif state=WaitForJump then
+        state <= Execute;
+        IPAddend <= x"00";
+        regIn(REGIP) <= JumpAddress;
       end if;
 
 
             when "0000" => --mov reg,imm
               regIn(to_integer(unsigned(bankreg1))) <= opimmd;
               regWE(to_integer(unsigned(bankreg1))) <= '1';
+              if(bankreg1="1111") then
+                    --FetchEN <= '0';
+                    --IPAddend <= x"00";
+                    --JumpAddress <= opimmd;
+                    --RegWE(REGIP) <= '0';
+                    --state <= WaitForJump;
+                  end if;
             when "0001" => --mov [reg],imm
               OpAddress <= regOut(REGDS) & regOut(to_integer(unsigned(bankreg1)));
               OpWE <= '1';
                       state <= WaitForMemory;
                       IPAddend <= x"00";
                       FetchEN <= '0';
+                    when "010" => --increment reg
+                      State <= WaitForAlu;
+                      IPAddend <= x"00";
+                      AluOp <= "10010";
+                      AluIn1 <= regOut(to_integer(unsigned(bankreg1)));
+                      AluIn2 <= x"00";
+                      AluRegOut <= bankreg1;
                     when others =>
                       --synthesis off
                       report "Not implemented subgroup 5-0" severity error;
                   end case;
                 when "001" => --mov reg, reg
                   regIn(to_integer(unsigned(bankreg1))) <= regOut(to_integer(unsigned(bankreg2)));
+                  if(bankreg1="1111") then
+                    FetchEN <= '0';
+                    IPAddend <= x"00";
+                    JumpAddress <= regOut(to_integer(unsigned(bankreg2)));
+                    --RegWE(REGIP) <= '0';
+                    state <= WaitForJump;
+                  end if;
                   regWE(to_integer(unsigned(bankreg1))) <= '1';
                 when "010" => --mov reg, [reg] (load)
                   OpDestReg1 <= bankreg1;
     WriteEnable: in std_logic;
     Clock: in std_logic;
     DataIn: in std_logic_vector(15 downto 0);
-    DataOut: out std_logic_vector(15 downto 0);
-
-    Port0: inout std_logic_vector(7 downto 0)
---    Reset: in std_logic
-    
-    --RAM/ROM interface (RAMA is built in to here
-    --RAMBDataIn: out std_logic_vector(15 downto 0);
-    --RAMBDataOut: in std_logic_vector(15 downto 0);
-    --RAMBAddress: out std_logic_vector(15 downto 0);
-    --RAMBWriteEnable: out std_logic_vector(1 downto 0);
+    DataOut: out std_logic_vector(15 downto 0)
   );
 end memory;
 
     );
   end component;
 
-  constant R1START: integer := 15;
-  constant R1END: integer := 1023+15;
+  constant R1START: integer := 0;
+  constant R1END: integer := 1023;
   signal addr: std_logic_vector(15 downto 0) := (others => '0');
   signal R1addr: std_logic_vector(7 downto 0);
   signal we: std_logic_vector(1 downto 0);
   signal R1in: std_logic_vector(15 downto 0);
   signal R1out: std_logic_vector(15 downto 0);
 
-  signal port0we: std_logic_vector(7 downto 0);
-  signal port0temp: std_logic_vector(7 downto 0);
-  signal port0out: std_logic_vector(7 downto 0);
-  signal port0in: std_logic_vector(7 downto 0);
   
 begin
   R1: blockram port map (R1addr, R1we, R1en, Clock, R1in, R1out);
 
 
-  gen2: for I in 0 to 7 generate
-    port0(I) <= port0out(I) when port0we(I)='1' else 'Z';
-    port0in(I) <= port0out(I) when port0we(I)='1' else port0(I);
-  end generate gen2;
 
   addrwe: process(Address, WriteWord, WriteEnable, DataIn)
   begin
     end if;
   end process;
   
-  assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address, Clock, port0temp, port0we, DataIn)
+  assignram: process (we, datawrite, addr, r1out,WriteEnable, Address, Clock, DataIn)
   variable tmp: integer;
-  variable tmp2: integer;
   variable found: boolean := false;
   begin
     tmp := to_integer(unsigned(addr));
-    tmp2 := to_integer(unsigned(Address));
-    if tmp2 <= 15 then --internal registers/mapped IO
-      if rising_edge(Clock) then
-        if WriteWord='0' then
-          if tmp2=0 then
-            --dataread <= x"0000";
-            
-            gen: for I in 0 to 7 loop
-              if WriteEnable='1' then
-                if port0we(I)='1' then --1-bit port set to WRITE mode
-                  
-                  Port0out(I) <= DataIn(I);
-                  if I=0 then
-                   -- report string(DataIn(I));
-                    --assert(DataIn(I)='1') report "XXXXX" severity note;
-                    --port0(I) <= '1';
-                  end if;
-                  port0temp(I) <= DataIn(I);
-                  --dataread(I) <= DataIn(I);
-                else
-                  port0out(I) <= '0';
-                  --port0(I) <= 'Z';
-                  --port0temp(I) <= '0';
-                  --dataread(I) <= port0(I);
-                end if;
-              end if;
-            end loop gen;
-          elsif tmp2=1 then
-            --dataread <= x"00" & port0we;
-            if WriteEnable='1' then
-              port0we <= DataIn(7 downto 0);
-              --dataread<=x"00" & DataIn(7 downto 0);
-              setwe: for I in 0 to 7 loop
-                if DataIn(I)='0' then
-                  --port0(I) <= 'Z';
-                  port0temp(I) <= '0';
-                else
-                  if port0temp(I)='0' then
-                    port0out(I) <= '0';
-                    port0temp(I) <= '0';
-                  else
-                    port0out(I) <= port0temp(I);
-                  end if;
-                end if;
-              end loop setwe;
-            else
-              --dataread <= x"00" & port0we;
-            end if;
-          else
-            --synthesis off
-            report "Memory address is outside of bounds of RAM and registers" severity warning;
-            --synthesis on
-          end if;
-        
-        else
-          --synthesis off
-          report "WriteWord is not allowed in register area. Ignoring access" severity warning;
-          --synthesis on
-        end if;
-      end if;
-      dataread <= x"00" & port0in;
---       outgen: for I in 0 to 7 loop
---         if tmp2=0 then
---           
---           if port0we(I)='1' then
---             if WriteEnable='1' then
---               dataread(I) <= DataIn(I);
---             else
---               dataread(I) <= port0temp(I);
---             end if;
---           else
---             if I=1 then
---               --assert(port0(I)='1') report "XXX" severity note;
---             end if;
---             if port0(I)='1' then
---               dataread(I) <= '1';
---             else
---               dataread(I) <= '0';
---             end if;
---             --dataread(I) <='1'; -- port0(I);
---           end if;
---         elsif tmp2=1 then
---           if WriteEnable='1' then
---             dataread(I) <= DataIn(I);
---           else
---             dataread(I) <= port0we(I);
---           end if;
---         else
---           dataread(I) <= '0';
---         end if;
---       end loop outgen;
-      R1en <= '0';
-      R1we <= "00";
-      R1in <= x"0000";
-      R1addr <= x"00";
-    elsif tmp >= R1START and tmp <= R1END then --RAM bank1
+    if tmp >= R1START and tmp <= R1END then --RAM bank1
       --map all to R1
       found := true;
       R1en <= '1';
     Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
     WriteEnable: in std_logic;
     Data: inout std_logic_vector(15 downto 0);
-    Port0: inout std_logic_vector(7 downto 0);
     --debug ports
     DebugR0: out std_logic_vector(7 downto 0)
   );
       WriteEnable: in std_logic;
       Clock: in std_logic;
       DataIn: in std_logic_vector(15 downto 0);
-      DataOut: out std_logic_vector(15 downto 0);
-      Port0: inout std_logic_vector(7 downto 0)
+      DataOut: out std_logic_vector(15 downto 0)
+      
     );
   end component;
 
     WriteEnable => MemWriteEnable,
     Clock => Clock,
     DataIn => MemDataIn,
-    DataOut => MemDataOut,
-    Port0 => Port0Temp --Port0
+    DataOut => MemDataOut
   );
   rom: bootrom port map(
     clk => clock,
     Addr => BootAddress,
     Data => BootDataOut
   );
-  Port0 <= Port0Temp when Reset='0' else x"FF";
   MemAddress <= cpuaddr when (DMA='0' and Reset='0') else BootMemAddress when (Reset='1' and DMA='0') else Address;
   MemWriteWord <= cpuww when DMA='0' and Reset='0' else '1' when Reset='1'  and DMA='0' else '1';
   MemWriteEnable <= cpuwe when DMA='0' and Reset='0' else'1'  when Reset='1' and DMA='0' else WriteEnable;

testbench/core_tb.vhd

     MemIn <= x"0056";
     wait for 10 ns;
     assert(DebugR0 = x"56") report "loaded value of R0 is not correct" severity error;
+
+    
+    MemIn <= "0101000000100000";
+    wait for 20 ns;
+    assert(DebugR0=x"57") report "incrementing R0 is not correct" severity error;
+    wait for 20 ns;
+    assert(DebugR0=x"58") report "double increment of R0 is not correct" severity error;
+    
+
     MemIn <= x"0E50"; --mov IP, 0x50
     wait for 10 ns; 
     assert( MemAddr = x"0150") report "mov to IP doesn't work" severity error; --DebugIP uses regOut, so it won't be updated until next clock cycle actually, but it's correct.

testbench/memory_tb.vhd

       WriteEnable: in std_logic;
       Clock: in std_logic;
       DataIn: in std_logic_vector(15 downto 0);
-      DataOut: out std_logic_vector(15 downto 0);
-      Port0: inout std_logic_vector(7 downto 0)
+      DataOut: out std_logic_vector(15 downto 0)
     );
   end component;
     
   --Outputs
   signal DataOut: std_logic_vector(15 downto 0);
 
-  --inouts
-  signal Port0: std_logic_vector(7 downto 0);
 
   signal Clock: std_logic;
   constant clock_period : time := 10 ns;
     WriteEnable => WriteEnable,
     Clock => Clock,
     DataIn => DataIn,
-    DataOut => DataOut,
-    Port0 => Port0
+    DataOut => DataOut
   );
 
   -- Clock process definitions
     wait for 10 ns;
     assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;
     
-    Address <= x"0001";
-    Port0 <= "ZZZZZZZ1";
-    WriteWord<='0';
-    WriteEnable <= '1';
-    DataIn <= x"00FE";
-    wait for 10 ns;
-    Address <= x"0000";
-    WriteEnable <= '1';
-    DataIn <= x"0000";
-    wait for 10 ns;
-    WriteEnable <= '0';
-    Address <= x"1234";
-    wait for 20 ns;
-    WriteEnable <= '1';
-    Address <= x"0000";
-    DataIn <= x"0001";
-    
-    wait for 10 ns;
-    WriteEnable <= '0';
-    assert(Port0(0)='1') report "port0 not right 1" severity error;
-    wait for 10 ns;
-    assert(DataOut(0)='1') report "port0 not right 2" severity error;
-    assert(DataOut=x"0001") report "full port0 not right 1" severity error;
-    assert(Port0=x"01") report "full port 0 not right 2" severity error;
+   
 
-
-    wait for 10 ns;
-    Address <= x"0001";
-    WriteWord <= '0';
-    WriteEnable <= '1';
-    DataIn <= b"00000000_0011_1000";
-    wait for 10 ns;
-    Address <= x"0000";
-    Port0 <= "10ZZZ101";
-    DataIn <= x"00" & b"00_101_011";
-    wait for 10 ns;
-    WriteEnable <= '0';
-    wait for 10 ns;
-    assert(Port0 = "10101101") report "Memory mapped port does not work correctly" severity error;
-    assert(DataOut = x"00" & "10101101") report "Memory read of mapped port does not work correctly" severity error;
     
 
    assert false

testbench/top_tb.vhd

       Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
       WriteEnable: in std_logic;
       Data: inout std_logic_vector(15 downto 0);
-      Port0: inout std_logic_vector(7 downto 0);
       --debug ports
       DebugR0: out std_logic_vector(7 downto 0)
     );
   signal Address: std_logic_vector(15 downto 0):=x"0000"; --memory address (in bytes)
   signal WriteEnable: std_logic:='0';
   signal Data: std_logic_vector(15 downto 0):=x"0000";
-  signal Port0: std_logic_vector(7 downto 0);
   --debug ports
   signal DebugR0: std_logic_vector(7 downto 0);
 
     Address => Address,
     WriteEnable => WriteEnable,
     Data => Data,
-    DebugR0 => DebugR0,
-    Port0 => Port0
+    DebugR0 => DebugR0
   );
 
   -- Clock process definitions
   stim_proc: process
     variable err_cnt: integer :=0;
   begin         
-    Port0 <= "ZZZZZZZZ";
-    Port0(1) <= '1';
     -- hold reset state for 100 ns.
     Reset <= '0';
     wait for 10 ns;
     
     wait for 50 ns;
     
-    wait for 200 ns;
-    assert(Port0(0)='1') report "Toggle app not working" severity error;
-    wait for 10 ns;
-    Port0(1) <= '0';
-    wait for 200 ns;
-    assert(Port0(0)='0') report "Toggle app not working 2" severity error;
+    wait for 500 ns;
+
 
 
 
     Hold <= '1';
     wait for 10 ns;
     assert (HoldAck ='1') report "HoldAck not becoming high" severity error;
-    --load memory image
-    DMA <= '1';
-    WriteEnable <= '1';
-    Address <= x"0100";
-    Data <= x"0057";
-    wait for 10 ns;
-    Address <= x"0102";
-    Data <= x"00F1";
-    wait for 10 ns;
-    Address <= x"0104";
-    Data <= x"00FF";
-    wait for 10 ns;
-    Address <= x"0106";
-    Data <= x"0063";
-    wait for 10 ns;
-    --Address <= x"0108";
-    --wait for 10 ns;
-    DMA <= '0';
-    wait for 10 ns;
-    Hold <= '0';
-    wait for 10 ns;
-    
-    --start the processor
-    Reset <= '0';
-    wait for 30 ns; --wait 3 clock cycles for CPU to execute first instruction
-    wait for 10 ns; --wait 1 clock cycle for first instruction decode
-    assert(Debugr0 = x"57") report "R0 is not loaded properly for first instruction" severity error;
-    wait for 10 ns;
-    assert(DebugR0 = x"F1") report "R0 is not loaded properly for second instruction" severity error;
+
+
     
 
 
Tip: Filter by directory path e.g. /media app.js to search for public/media/app.js.
Tip: Use camelCasing e.g. ProjME to search for ProjectModifiedEvent.java.
Tip: Filter by extension type e.g. /repo .js to search for all .js files in the /repo directory.
Tip: Separate your search with spaces e.g. /ssh pom.xml to search for src/ssh/pom.xml.
Tip: Use ↑ and ↓ arrow keys to navigate and return to view the file.
Tip: You can also navigate files with Ctrl+j (next) and Ctrl+k (previous) and view the file with Ctrl+o.
Tip: You can also navigate files with Alt+j (next) and Alt+k (previous) and view the file with Alt+o.