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Trammell Hudson  committed 94a2e4c Draft

works with teensy backpack

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  • Parent commits 8f95de1

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File alphawatch.c

 }
 
 
-#define ADDR_0	0xF0
-#define ADDR_1	0xF1
-#define ADDR_2	0xF4
-#define ADDR_3	0xF5
-#define ADDR_4	0xF6
+#define ADDR_0	0xF4
+#define ADDR_1	0xF5
+#define ADDR_2	0xF6
+#define ADDR_3	0xF7
+#define ADDR_4	0xD7
 
-#define DATA_0	0xB0
-#define DATA_1	0xB1
-#define DATA_2	0xB2
-#define DATA_3	0xB3
-#define DATA_4	0xD0
-#define DATA_5	0xD1
-#define DATA_6	0xD2
-#define DATA_7	0xD3
+#define DATA_0	0xC6
+#define DATA_1	0xD3
+#define DATA_2	0xD0
+#define DATA_3	0xB7
+#define DATA_4	0xB3
+#define DATA_5	0xB2
+#define DATA_6	0xB1
+#define DATA_7	0xB0
 
-#define CE	0xF7
-#define RESET	0xB6
+#define FLASH	0xF1
+#define RESET	0xF0
+#define WRCE	0xD5
+#define RD	0xC7
+#define CLKSEL	0xD6
 
 
 
 	out(DATA_7, data & 1); data >>= 1;
 
 	//_delay_us(100);
-	out(CE, 0);
+	out(WRCE, 0);
 	_delay_us(10);
-	out(CE, 1);
+	out(WRCE, 1);
 }
 
 int
 	ddr(ADDR_3, 1);
 	ddr(ADDR_4, 1);
 
-	ddr(CE, 1);
+	// !FLASH should be high to select normal memory
+	out(FLASH, 1);
+	ddr(FLASH, 1);
+
+	// CLS should be high to select internal clocks
+	out(CLKSEL, 1);
+	ddr(CLKSEL, 1);
+
+	// WRCE ties together !WR and !CE
+	out(WRCE, 1);
+	ddr(WRCE, 1);
+
+	out(RESET, 1);
 	ddr(RESET, 1);
 
-	out(CE, 1);
-	out(RESET, 1);
-
+	// Reset the display
 	_delay_ms(100);
 	out(RESET, 0);
 	_delay_ms(10);