Overview
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mMips in MyHDL
This mMips in MyHDL is used in course 5JJ55 on TU/e. Few implementation variants are available now:
- A single cycle mini-mini MIPS
- A pipelined, multicycle mini MIPS
You can simulate the mMips and generate VHDL and/or Verilog.
Prerequisites: python with MyHDL
Single Cycle Mini-mini MIPS
Typical usage:
#!/usr/bin/env python from myhdl import * from single_cycle_mmmips.sc_mmmips import sc_mmmips
if __name__ == "__main__":
clk = Signal(bool(0)) mips_inst = toVerilog(sc_mmmips, clk) print "sc_mmmips generated"
- def testbench():
clk = Signal(bool(0)) halfPeriod = delay(5)
@always(halfPeriod) def driveClk():
clk.next = not clk if clk:
print "Time:", now()i_mips = sc_mmmips(clk)
return instances()
# Initialization (automatically done, now, with default filenames) # Files could be specified at instantiation, if needed #i_pmem.init("mips_rom.bin"); #i_dmem.init("mips_ram.bin");
tb = traceSignals(testbench) sim = Simulation(tb) sim.run(200)
return
A synthesizable Mini MIPS
Typical usage often looks like this:
#!/usr/bin/env python
from mmips.testbench import testbench
- if __name__ == "__main__":
clk = Signal(bool(0)) rst = Signal(bool(0)) enable = Signal(bool(1)) # Enable the system period = 10 # clock period in ns
def main():
tb = testbench(clk, enable, rst)
@The Instance def clkgen():
yield delay(period // 2) clk.next = not clk@always(clk.posedge) def stop():
- if now() > 2300:
- print now() raise StopSimulation
return instances()
tb = traceSignals(main) sim = Simulation(tb) sim.run()
veri = toVerilog(testbench, clk, enable, rst) print "testbench generated in verilog"
vhdl = toVHDL(testbench, clk, enable, rst) print "testbench generated in VHDL"
Before running a simulation the memory of the processor needs to be initialized with code and data. For now a binary file named "mips_mem.bin" needs to be present in the run directory.
Compiler
Compiler and disassembler are available from TU/e http://www.es.ele.tue.nl/education/5JJ55-65. You need 'lcc' to generate binary images to enable simulation.
Contributors
S.Stuijk and A.S.Slusarczyk for producing the original SystemC model for the TU/e course 5JJ55-65 http://www.es.ele.tue.nl/education/5JJ55-65.
Thanks also to
Jan Decaluwe, for creating MyHDL http://www.myhdl.org.