RISC-V compiler and linker corrections

Branch: millerresearch/inferno-riscv:utils-riscv

Branch: inferno-os/inferno-os:master

Merged

#10 · Created 2020-12-08 · Last updated 2021-03-07

Merged pull request

Merged in utils-riscv (pull request #10)

29b38a8·Author: Richard Miller·Closed by: Charles Forsyth·2021-03-07

Description

jc: use MOVWU for unsigned int register load
jc: fix opcode for vlong shifts
il: align data segment between small and large vars

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