Commits

iorodeo  committed 07ef097 Draft

Fixed some issues - pads too small, mislabeled DIO.

  • Participants
  • Parent commits 7442a60

Comments (0)

Files changed (11)

File Arduino_Shields_CONN13.mod

-PCBNEW-LibModule-V1  Mon 24 Sep 2012 10:29:46 AM PDT
+PCBNEW-LibModule-V1  Fri 23 Aug 2013 05:55:27 PM PDT
 # encoding utf-8
+Units mm
 $INDEX
 CONN_13
 $EndINDEX
 $MODULE CONN_13
-Po 0 0 0 15 50609884 00000000 ~~
+Po 0 0 0 15 5218047B 00000000 ~~
 Li CONN_13
-Sc 00000000
+Sc 0
 AR CONN_13
 Op 0 0 0
-T0 -4843 -2047 600 600 0 120 N V 21 N "CONN_13"
-T1 0 -2008 600 600 0 120 N V 21 N "VAL**"
-DS 9174 -1417 -9173 -1417 150 21
-DS 9173 1377 -9173 1377 150 21
-DS -9174 -1418 -9174 1338 150 21
-DS 9175 -1417 9175 1378 150 21
+T0 -12.30122 -5.19938 1.524 1.524 0 0.3048 N V 21 N "CONN_13"
+T1 0 -5.10032 1.524 1.524 0 0.3048 N V 21 N "VAL**"
+DS 23.30196 -3.59918 -23.29942 -3.59918 0.381 21
+DS 23.29942 3.49758 -23.29942 3.49758 0.381 21
+DS -23.30196 -3.60172 -23.30196 3.39852 0.381 21
+DS 23.3045 -3.59918 23.3045 3.50012 0.381 21
 $PAD
-Sh "1" C 600 600 0 0 1800
-Dr 354 0 0
+Sh "1" O 1.651 2.54 0 0 1800
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po -8269 1
+Po -21.00326 0.00254
 $EndPAD
 $PAD
-Sh "2" C 600 600 0 0 1800
-Dr 354 0 0
+Sh "2" O 1.651 2.54 0 0 1800
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po -6892 0
+Po -17.50568 0
 $EndPAD
 $PAD
-Sh "3" C 600 600 0 0 1800
-Dr 354 0 0
+Sh "3" O 1.651 2.54 0 0 1800
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po -5511 -1
+Po -13.99794 -0.00254
 $EndPAD
 $PAD
-Sh "4" C 600 600 0 0 1800
-Dr 354 0 0
+Sh "4" O 1.651 2.54 0 0 1800
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po -4134 0
+Po -10.50036 0
 $EndPAD
 $PAD
-Sh "5" C 600 600 0 0 1800
-Dr 354 0 0
+Sh "5" O 1.651 2.54 0 0 1800
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po -2756 0
+Po -7.00024 0
 $EndPAD
 $PAD
-Sh "6" C 600 600 0 0 1800
-Dr 354 0 0
+Sh "6" O 1.651 2.54 0 0 1800
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po -1380 0
+Po -3.5052 0
 $EndPAD
 $PAD
-Sh "7" C 600 600 0 0 1800
-Dr 354 0 0
+Sh "7" O 1.651 2.54 0 0 1800
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po -1 0
+Po -0.00254 0
 $EndPAD
 $PAD
-Sh "8" C 600 600 0 0 0
-Dr 354 0 0
+Sh "8" O 1.651 2.54 0 0 0
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po 1377 -1
+Po 3.49758 -0.00254
 $EndPAD
 $PAD
-Sh "9" C 600 600 0 0 0
-Dr 354 0 0
+Sh "9" O 1.651 2.54 0 0 0
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po 2755 -1
+Po 6.9977 -0.00254
 $EndPAD
 $PAD
-Sh "10" C 600 600 0 0 0
-Dr 354 0 0
+Sh "10" O 1.651 2.54 0 0 0
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po 4135 -1
+Po 10.5029 -0.00254
 $EndPAD
 $PAD
-Sh "12" C 600 600 0 0 0
-Dr 354 0 0
+Sh "12" O 1.651 2.54 0 0 0
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po 6889 -2
+Po 17.49806 -0.00508
 $EndPAD
 $PAD
-Sh "11" C 600 600 0 0 0
-Dr 354 0 0
+Sh "11" O 1.651 2.54 0 0 0
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po 5511 -1
+Po 13.99794 -0.00254
 $EndPAD
 $PAD
-Sh "13" C 600 600 0 0 1800
-Dr 354 0 0
+Sh "13" O 1.651 2.54 0 0 1800
+Dr 0.89916 0 0
 At STD N 00E0FFFF
 Ne 0 ""
-Po 8267 -1
+Po 20.99818 -0.00254
 $EndPAD
-$EndMODULE  CONN_13
+$EndMODULE CONN_13
 $EndLIBRARY

File C1_BIG_PAD.mod

+PCBNEW-LibModule-V1  Fri 23 Aug 2013 06:00:10 PM PDT
+# encoding utf-8
+Units mm
+$INDEX
+C1_Big_Pad
+$EndINDEX
+$MODULE C1_Big_Pad
+Po 0 0 0 15 5218054E 00000000 ~~
+Li C1_Big_Pad
+Cd Condensateur e = 1 pas
+Kw C
+Sc 0
+AR 
+Op 0 0 0
+T0 0.254 -2.286 1.016 1.016 0 0.2032 N V 21 N "C1"
+T1 0 -2.286 1.016 1.016 0 0.2032 N I 21 N "V***"
+DS -2.4892 -1.27 2.54 -1.27 0.3048 21
+DS 2.54 -1.27 2.54 1.27 0.3048 21
+DS 2.54 1.27 -2.54 1.27 0.3048 21
+DS -2.54 1.27 -2.54 -1.27 0.3048 21
+DS -2.54 -0.635 -1.905 -1.27 0.3048 21
+$PAD
+Sh "1" C 1.651 1.651 0 0 0
+Dr 0.8128 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -1.27 0
+$EndPAD
+$PAD
+Sh "2" C 1.651 1.651 0 0 0
+Dr 0.8128 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 1.27 0
+$EndPAD
+$SHAPE3D
+Na "discret/capa_1_pas.wrl"
+Sc 1 1 1
+Of 0 0 0
+Ro 0 0 0
+$EndSHAPE3D
+$EndMODULE C1_Big_Pad
+$EndLIBRARY

File C2_BIG_PAD.mod

+PCBNEW-LibModule-V1  Fri 23 Aug 2013 06:07:26 PM PDT
+# encoding utf-8
+Units mm
+$INDEX
+C2_Big_Pad
+$EndINDEX
+$MODULE C2_Big_Pad
+Po 0 0 0 15 5218064A 00000000 ~~
+Li C2_Big_Pad
+Cd Condensateur = 2 pas
+Kw C
+Sc 0
+AR 
+Op 0 0 0
+T0 0 0 1.016 1.016 0 0.2032 N V 21 N "C2"
+T1 0 0 1.016 1.016 0 0.2032 N I 21 N "C***"
+DS -3.556 -1.016 3.556 -1.016 0.3048 21
+DS 3.556 -1.016 3.556 1.016 0.3048 21
+DS 3.556 1.016 -3.556 1.016 0.3048 21
+DS -3.556 1.016 -3.556 -1.016 0.3048 21
+DS -3.556 -0.508 -3.048 -1.016 0.3048 21
+$PAD
+Sh "1" C 1.651 1.651 0 0 0
+Dr 0.8128 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -2.54 0
+$EndPAD
+$PAD
+Sh "2" C 1.651 1.651 0 0 0
+Dr 0.8128 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 2.54 0
+$EndPAD
+$SHAPE3D
+Na "discret/capa_2pas_5x5mm.wrl"
+Sc 1 1 1
+Of 0 0 0
+Ro 0 0 0
+$EndSHAPE3D
+$EndMODULE C2_Big_Pad
+$EndLIBRARY

File ana_in_shield.cmp

-Cmp-Mod V01 Created by CvPCB (2011-05-25)-stable date = Mon 16 Jul 2012 01:35:56 PM PDT
+Cmp-Mod V01 Created by CvPcb (2013-mar-13)-testing date = Fri 23 Aug 2013 06:14:26 PM PDT
 
 BeginCmp
 TimeStamp = /4D1E88FA;
-Reference = C11;
+Reference = C1;
 ValeurCmp = 4.7uF;
-IdModule  = C2;
+IdModule  = C2_Big_Pad;
 EndCmp
 
 BeginCmp
 TimeStamp = /4D1E8852;
-Reference = C12;
+Reference = C2;
 ValeurCmp = 0.1uF;
-IdModule  = C2;
+IdModule  = C2_Big_Pad;
 EndCmp
 
 BeginCmp
 TimeStamp = /4D1E88E9;
-Reference = C13;
+Reference = C3;
 ValeurCmp = 0.01uF;
-IdModule  = C1;
+IdModule  = C1_Big_Pad;
 EndCmp
 
 BeginCmp
 TimeStamp = /4D2273C2;
-Reference = C14;
+Reference = C4;
 ValeurCmp = 4.7uF;
-IdModule  = C2;
+IdModule  = C2_Big_Pad;
 EndCmp
 
 BeginCmp
 TimeStamp = /4D1E7C35;
 Reference = U8;
 ValeurCmp = MAX1270-PDIP;
-IdModule  = DIP-24__300;
+IdModule  = DIP-24__300_ELL;
 EndCmp
 
 EndListe

File ana_in_shield.dsn

   (parser
     (string_quote ")
     (space_in_quoted_tokens on)
-    (host_cad "Kicad's PCBNEW")
-    (host_version "(2011-aug-04)-testing")
+    (host_cad "KiCad's Pcbnew")
+    (host_version "(2013-mar-13)-testing")
   )
-  (resolution mil 10)
-  (unit mil)
+  (resolution um 10)
+  (unit um)
   (structure
     (layer Front
       (type signal)
       )
     )
     (boundary
-      (path pcb 0  4872 -5267.7  7622 -5267.7  7622 -3167.3  4872 -3167.3
-            4872 -5267.7)
+      (path pcb 0  123749 -133800  196139 -133800  196139 -80449.4  123749 -80449.4
+            123749 -133800)
     )
-    (via "Via[0-1]_35:25_mil" "Via[0-1]_35:0_mil")
+    (via "Via[0-1]_889:635_um" "Via[0-1]_889:0_um")
     (rule
-      (width 15)
-      (clearance 10.1)
-      (clearance 10.1 (type default_smd))
-      (clearance 2.5 (type smd_smd))
+      (width 508)
+      (clearance 254.1)
+      (clearance 254.1 (type default_smd))
+      (clearance 63.5 (type smd_smd))
     )
   )
   (placement
     (component ARDUINO_SHIELD
-      (place SHIELD1 4523.7 -5267.7 front 0 (PN ARDUINO_SHIELD))
+      (place SHIELD1 114902 -133800 front 0 (PN ARDUINO_SHIELD))
     )
-    (component "DIP-24__300"
-      (place U8 6245.1 -4217.5 front 180 (PN "MAX1270-PDIP"))
-    )
-    (component C2
-      (place C11 6726.4 -4628 front 270 (PN 4.7uF))
-      (place C12 6789.4 -3781.5 front 90 (PN 0.1uF))
-      (place C14 6608.3 -3777.6 front 90 (PN 4.7uF))
-    )
-    (component C1
-      (place C13 6468.5 -4592.5 front 270 (PN 0.01uF))
+    (component "DIP-24__300_ELL"
+      (place U8 158500 -107112 front 180 (PN "MAX1270-PDIP"))
     )
     (component CONN_13
-      (place P1 7484.2 -4217.5 front 90 (PN CONN_13))
+      (place P1 192639 -107124 front 90 (PN CONN_13))
+    )
+    (component C1_Big_Pad
+      (place C3 164550 -118220 front 270 (PN 0.01uF))
+    )
+    (component C2_Big_Pad
+      (place C1 170150 -118240 front 270 (PN 4.7uF))
+      (place C2 174960 -94340 front 90 (PN 0.1uF))
+      (place C4 169470 -94340 front 90 (PN 4.7uF))
     )
   )
   (library
     (image ARDUINO_SHIELD
-      (pin Oval[A]Pad_100x60_mil (rotate 90) AD5 2500 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) AD4 2400 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) AD3 2300 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) AD0 2000 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) AD1 2100 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) AD2 2200 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) V_IN 1800 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) GND2 1700 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) GND1 1600 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 3V3 1400 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) RST 1300 100)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 0 2500 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 1 2400 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 2 2300 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 3 2200 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 4 2100 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 5 2000 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 6 1900 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 7 1800 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 8 1640 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 9 1540 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 10 1440 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 11 1340 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 12 1240 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 13 1140 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) GND3 1040 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) AREF 940 2000)
-      (pin Oval[A]Pad_100x60_mil (rotate 90) 5V 1500 100)
-      (pin Round[A]Pad_155_mil (rotate 90) @1 2600 300)
-      (pin Round[A]Pad_155_mil (rotate 90) @2 2600 1400)
-      (pin Round[A]Pad_155_mil (rotate 90) @3 600 2000)
-      (pin Round[A]Pad_155_mil (rotate 90) @4 550 100)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) AD5 63500 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) AD4 60960 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) AD3 58420 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) AD0 50800 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) AD1 53340 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) AD2 55880 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) V_IN 45720 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) GND2 43180 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) GND1 40640 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 3V3 35560 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) RST 33020 2540)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 0 63500 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 1 60960 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 2 58420 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 3 55880 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 4 53340 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 5 50800 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 6 48260 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 7 45720 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 8 41656 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 9 39116 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 10 36576 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 11 34036 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 12 31496 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 13 28956 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) GND3 26416 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) AREF 23876 50800)
+      (pin Oval[A]Pad_2540x1524_um (rotate 90) 5V 38100 2540)
+      (pin Round[A]Pad_3937_um (rotate 90) @1 66040 7620)
+      (pin Round[A]Pad_3937_um (rotate 90) @2 66040 35560)
+      (pin Round[A]Pad_3937_um (rotate 90) @3 15240 50800)
+      (pin Round[A]Pad_3937_um (rotate 90) @4 13970 2540)
     )
-    (image "DIP-24__300"
-      (outline (path signal 15  -650 50  -600 50))
-      (outline (path signal 15  -600 50  -600 -50))
-      (outline (path signal 15  -600 -50  -650 -50))
-      (outline (path signal 15  -650 -50  -650 -50))
-      (outline (path signal 15  -650 100  650 100))
-      (outline (path signal 15  650 100  650 -100))
-      (outline (path signal 15  650 -100  -650 -100))
-      (outline (path signal 15  -650 -100  -650 100))
-      (pin Rect[A]Pad_55x55_mil 1 -550 -150)
-      (pin Round[A]Pad_55_mil 2 -450 -150)
-      (pin Round[A]Pad_55_mil 3 -350 -150)
-      (pin Round[A]Pad_55_mil 4 -250 -150)
-      (pin Round[A]Pad_55_mil 5 -150 -150)
-      (pin Round[A]Pad_55_mil 6 -50 -150)
-      (pin Round[A]Pad_55_mil 7 50 -150)
-      (pin Round[A]Pad_55_mil 8 150 -150)
-      (pin Round[A]Pad_55_mil 9 250 -150)
-      (pin Round[A]Pad_55_mil 10 350 -150)
-      (pin Round[A]Pad_55_mil 11 450 -150)
-      (pin Round[A]Pad_55_mil 12 550 -150)
-      (pin Round[A]Pad_55_mil 13 550 150)
-      (pin Round[A]Pad_55_mil 14 450 150)
-      (pin Round[A]Pad_55_mil 15 350 150)
-      (pin Round[A]Pad_55_mil 16 250 150)
-      (pin Round[A]Pad_55_mil 17 150 150)
-      (pin Round[A]Pad_55_mil 18 50 150)
-      (pin Round[A]Pad_55_mil 19 -50 150)
-      (pin Round[A]Pad_55_mil 20 -150 150)
-      (pin Round[A]Pad_55_mil 21 -250 150)
-      (pin Round[A]Pad_55_mil 22 -350 150)
-      (pin Round[A]Pad_55_mil 23 -450 150)
-      (pin Round[A]Pad_55_mil 24 -550 150)
-    )
-    (image C2
-      (outline (path signal 12  -140 40  140 40))
-      (outline (path signal 12  140 40  140 -40))
-      (outline (path signal 12  140 -40  -140 -40))
-      (outline (path signal 12  -140 -40  -140 40))
-      (outline (path signal 12  -140 20  -120 40))
-      (pin Round[A]Pad_55_mil 1 -100 0)
-      (pin Round[A]Pad_55_mil 2 100 0)
-    )
-    (image C1
-      (outline (path signal 12  -98 50  100 50))
-      (outline (path signal 12  100 50  100 -50))
-      (outline (path signal 12  100 -50  -100 -50))
-      (outline (path signal 12  -100 -50  -100 50))
-      (outline (path signal 12  -100 25  -75 50))
-      (pin Round[A]Pad_55_mil 1 -50 0)
-      (pin Round[A]Pad_55_mil 2 50 0)
+    (image "DIP-24__300_ELL"
+      (outline (path signal 381  -16510 1270  -15240 1270))
+      (outline (path signal 381  -15240 1270  -15240 -1270))
+      (outline (path signal 381  -15240 -1270  -16510 -1270))
+      (outline (path signal 381  -16510 -1270  -16510 -1270))
+      (outline (path signal 381  -16510 2540  16510 2540))
+      (outline (path signal 381  16510 2540  16510 -2540))
+      (outline (path signal 381  16510 -2540  -16510 -2540))
+      (outline (path signal 381  -16510 -2540  -16510 2540))
+      (pin Rect[A]Pad_1574.8x2286_um 1 -13970 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 2 -11430 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 3 -8890 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 4 -6350 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 5 -3810 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 6 -1270 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 7 1270 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 8 3810 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 9 6350 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 10 8890 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 11 11430 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 12 13970 -3810)
+      (pin Oval[A]Pad_1574.8x2286_um 13 13970 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 14 11430 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 15 8890 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 16 6350 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 17 3810 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 18 1270 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 19 -1270 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 20 -3810 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 21 -6350 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 22 -8890 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 23 -11430 3810)
+      (pin Oval[A]Pad_1574.8x2286_um 24 -13970 3810)
     )
     (image CONN_13
-      (outline (path signal 15  917.4 141.7  -917.3 141.7))
-      (outline (path signal 15  917.3 -137.7  -917.3 -137.7))
-      (outline (path signal 15  -917.4 141.8  -917.4 -133.8))
-      (outline (path signal 15  917.5 141.7  917.5 -137.8))
-      (pin Round[A]Pad_60_mil (rotate 180) 1 -826.9 -0.1)
-      (pin Round[A]Pad_60_mil (rotate 180) 2 -689.2 0)
-      (pin Round[A]Pad_60_mil (rotate 180) 3 -551.1 0.1)
-      (pin Round[A]Pad_60_mil (rotate 180) 4 -413.4 0)
-      (pin Round[A]Pad_60_mil (rotate 180) 5 -275.6 0)
-      (pin Round[A]Pad_60_mil (rotate 180) 6 -138 0)
-      (pin Round[A]Pad_60_mil (rotate 180) 7 -0.1 0)
-      (pin Round[A]Pad_60_mil 8 137.7 0.1)
-      (pin Round[A]Pad_60_mil 9 275.5 0.1)
-      (pin Round[A]Pad_60_mil 10 413.5 0.1)
-      (pin Round[A]Pad_60_mil 12 688.9 0.2)
-      (pin Round[A]Pad_60_mil 11 551.1 0.1)
-      (pin Round[A]Pad_60_mil (rotate 180) 13 826.7 0.1)
+      (outline (path signal 381  23302 3599.18  -23299.4 3599.18))
+      (outline (path signal 381  23299.4 -3497.58  -23299.4 -3497.58))
+      (outline (path signal 381  -23302 3601.72  -23302 -3398.52))
+      (outline (path signal 381  23304.5 3599.18  23304.5 -3500.12))
+      (pin Oval[A]Pad_1651x2540_um (rotate 180) 1 -21003.3 -2.54)
+      (pin Oval[A]Pad_1651x2540_um (rotate 180) 2 -17505.7 0)
+      (pin Oval[A]Pad_1651x2540_um (rotate 180) 3 -13997.9 2.54)
+      (pin Oval[A]Pad_1651x2540_um (rotate 180) 4 -10500.4 0)
+      (pin Oval[A]Pad_1651x2540_um (rotate 180) 5 -7000.24 0)
+      (pin Oval[A]Pad_1651x2540_um (rotate 180) 6 -3505.2 0)
+      (pin Oval[A]Pad_1651x2540_um (rotate 180) 7 -2.54 0)
+      (pin Oval[A]Pad_1651x2540_um 8 3497.58 2.54)
+      (pin Oval[A]Pad_1651x2540_um 9 6997.7 2.54)
+      (pin Oval[A]Pad_1651x2540_um 10 10502.9 2.54)
+      (pin Oval[A]Pad_1651x2540_um 12 17498.1 5.08)
+      (pin Oval[A]Pad_1651x2540_um 11 13997.9 2.54)
+      (pin Oval[A]Pad_1651x2540_um (rotate 180) 13 20998.2 2.54)
     )
-    (padstack Round[A]Pad_155_mil
-      (shape (circle Front 155))
-      (shape (circle Back 155))
+    (image C1_Big_Pad
+      (outline (path signal 304.8  -2489.2 1270  2540 1270))
+      (outline (path signal 304.8  2540 1270  2540 -1270))
+      (outline (path signal 304.8  2540 -1270  -2540 -1270))
+      (outline (path signal 304.8  -2540 -1270  -2540 1270))
+      (outline (path signal 304.8  -2540 635  -1905 1270))
+      (pin Round[A]Pad_1651_um 1 -1270 0)
+      (pin Round[A]Pad_1651_um 2 1270 0)
+    )
+    (image C2_Big_Pad
+      (outline (path signal 304.8  -3556 1016  3556 1016))
+      (outline (path signal 304.8  3556 1016  3556 -1016))
+      (outline (path signal 304.8  3556 -1016  -3556 -1016))
+      (outline (path signal 304.8  -3556 -1016  -3556 1016))
+      (outline (path signal 304.8  -3556 508  -3048 1016))
+      (pin Round[A]Pad_1651_um 1 -2540 0)
+      (pin Round[A]Pad_1651_um 2 2540 0)
+    )
+    (padstack Round[A]Pad_1651_um
+      (shape (circle Front 1651))
+      (shape (circle Back 1651))
       (attach off)
     )
-    (padstack Round[A]Pad_55_mil
-      (shape (circle Front 55))
-      (shape (circle Back 55))
+    (padstack Round[A]Pad_3937_um
+      (shape (circle Front 3937))
+      (shape (circle Back 3937))
       (attach off)
     )
-    (padstack Round[A]Pad_60_mil
-      (shape (circle Front 60))
-      (shape (circle Back 60))
+    (padstack Oval[A]Pad_2540x1524_um
+      (shape (path Front 1524  -508 0  508 0))
+      (shape (path Back 1524  -508 0  508 0))
       (attach off)
     )
-    (padstack Oval[A]Pad_100x60_mil
-      (shape (path Front 60  -20 0  20 0))
-      (shape (path Back 60  -20 0  20 0))
+    (padstack Oval[A]Pad_1574.8x2286_um
+      (shape (path Front 1574.8  0 -355.6  0 355.6))
+      (shape (path Back 1574.8  0 -355.6  0 355.6))
       (attach off)
     )
-    (padstack Rect[A]Pad_55x55_mil
-      (shape (rect Front -27.5 -27.5 27.5 27.5))
-      (shape (rect Back -27.5 -27.5 27.5 27.5))
+    (padstack Oval[A]Pad_1651x2540_um
+      (shape (path Front 1651  0 -444.5  0 444.5))
+      (shape (path Back 1651  0 -444.5  0 444.5))
       (attach off)
     )
-    (padstack "Via[0-1]_35:25_mil"
-      (shape (circle Front 35))
-      (shape (circle Back 35))
+    (padstack Rect[A]Pad_1574.8x2286_um
+      (shape (rect Front -787.4 -1143 787.4 1143))
+      (shape (rect Back -787.4 -1143 787.4 1143))
       (attach off)
     )
-    (padstack "Via[0-1]_35:0_mil"
-      (shape (circle Front 35))
-      (shape (circle Back 35))
+    (padstack "Via[0-1]_889:635_um"
+      (shape (circle Front 889))
+      (shape (circle Back 889))
+      (attach off)
+    )
+    (padstack "Via[0-1]_889:0_um"
+      (shape (circle Front 889))
+      (shape (circle Back 889))
       (attach off)
     )
   )
   (network
     (net /5V
-      (pins SHIELD1-5V U8-1 U8-11 C12-1 C14-1)
+      (pins SHIELD1-5V U8-1 U8-11 C2-1 C4-1)
     )
     (net /CH0
       (pins U8-13 P1-1)
       (pins SHIELD1-8 U8-8)
     )
     (net GND
-      (pins SHIELD1-GND1 U8-2 U8-4 U8-12 C11-2 C12-2 C14-2 C13-2 P1-13)
+      (pins SHIELD1-GND1 U8-2 U8-4 U8-12 P1-13 C3-2 C1-2 C2-2 C4-2)
+    )
+    (net "N-000001"
+      (pins SHIELD1-GND3)
+    )
+    (net "N-0000011"
+      (pins SHIELD1-9)
+    )
+    (net "N-0000012"
+      (pins SHIELD1-AD0)
+    )
+    (net "N-0000013"
+      (pins SHIELD1-AD1)
+    )
+    (net "N-0000014"
+      (pins SHIELD1-AD2)
+    )
+    (net "N-0000015"
+      (pins SHIELD1-AD3)
+    )
+    (net "N-0000016"
+      (pins SHIELD1-3V3)
+    )
+    (net "N-0000017"
+      (pins SHIELD1-AD4)
+    )
+    (net "N-0000018"
+      (pins SHIELD1-AD5)
+    )
+    (net "N-0000019"
+      (pins SHIELD1-RST)
+    )
+    (net "N-000002"
+      (pins SHIELD1-AREF)
+    )
+    (net "N-0000020"
+      (pins SHIELD1-GND2)
+    )
+    (net "N-0000022"
+      (pins U8-3)
+    )
+    (net "N-0000024"
+      (pins U8-9)
+    )
+    (net "N-0000026"
+      (pins U8-21 C3-1)
+    )
+    (net "N-0000027"
+      (pins U8-22)
+    )
+    (net "N-0000028"
+      (pins U8-23 C1-1)
+    )
+    (net "N-0000029"
+      (pins U8-24)
     )
     (net "N-000003"
-      (pins U8-21 C13-1)
+      (pins SHIELD1-V_IN)
     )
-    (net "N-000026"
-      (pins U8-23 C11-1)
+    (net "N-000004"
+      (pins SHIELD1-0)
+    )
+    (net "N-000005"
+      (pins SHIELD1-1)
+    )
+    (net "N-000007"
+      (pins SHIELD1-4)
+    )
+    (net "N-000009"
+      (pins SHIELD1-7)
     )
     (class kicad_default "" /5V /CH0 /CH1 /CH2 /CH3 /CH4 /CH5 /CH6 /CH7 /CS0
-      /D2 /D3 /D5 /D6 /MISO /MOSI /SCK /SSTRB GND "N-000003" "N-000026"
+      /D2 /D3 /D5 /D6 /MISO /MOSI /SCK /SSTRB GND "N-000001" "N-0000011" "N-0000012"
+      "N-0000013" "N-0000014" "N-0000015" "N-0000016" "N-0000017" "N-0000018"
+      "N-0000019" "N-000002" "N-0000020" "N-0000022" "N-0000024" "N-0000026"
+      "N-0000027" "N-0000028" "N-0000029" "N-000003" "N-000004" "N-000005"
+      "N-000007" "N-000009"
       (circuit
-        (use_via Via[0-1]_35:25_mil)
+        (use_via Via[0-1]_889:635_um)
       )
       (rule
-        (width 15)
-        (clearance 10.1)
+        (width 508)
+        (clearance 254.1)
       )
     )
   )

File ana_in_shield.kicad_pcb

+(kicad_pcb (version 3) (host pcbnew "(2013-mar-13)-testing")
+
+  (general
+    (links 31)
+    (no_connects 0)
+    (area 123.558299 80.258919 196.329301 133.990081)
+    (thickness 1.6002)
+    (drawings 51)
+    (tracks 114)
+    (zones 0)
+    (modules 7)
+    (nets 43)
+  )
+
+  (page A4)
+  (title_block
+    (date "24 sep 2012")
+  )
+
+  (layers
+    (15 Front signal)
+    (0 Back signal)
+    (16 B.Adhes user)
+    (17 F.Adhes user)
+    (18 B.Paste user)
+    (19 F.Paste user)
+    (20 B.SilkS user)
+    (21 F.SilkS user)
+    (22 B.Mask user)
+    (23 F.Mask user)
+    (24 Dwgs.User user)
+    (25 Cmts.User user)
+    (26 Eco1.User user)
+    (27 Eco2.User user)
+    (28 Edge.Cuts user)
+  )
+
+  (setup
+    (last_trace_width 0.508)
+    (trace_clearance 0.254)
+    (zone_clearance 0.254)
+    (zone_45_only no)
+    (trace_min 0.2032)
+    (segment_width 0.381)
+    (edge_width 0.381)
+    (via_size 0.889)
+    (via_drill 0.635)
+    (via_min_size 0.889)
+    (via_min_drill 0.508)
+    (uvia_size 0.508)
+    (uvia_drill 0.127)
+    (uvias_allowed no)
+    (uvia_min_size 0.508)
+    (uvia_min_drill 0.127)
+    (pcb_text_width 0.3048)
+    (pcb_text_size 1.524 2.032)
+    (mod_edge_width 0.381)
+    (mod_text_size 1.524 1.524)
+    (mod_text_width 0.3048)
+    (pad_size 1.651 1.651)
+    (pad_drill 0.8128)
+    (pad_to_mask_clearance 0.254)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 284196865)
+      (usegerberextensions true)
+      (excludeedgelayer true)
+      (linewidth 0.150000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15)
+      (hpglpenoverlay 0)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotothertext true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 /5V)
+  (net 2 /CH0)
+  (net 3 /CH1)
+  (net 4 /CH2)
+  (net 5 /CH3)
+  (net 6 /CH4)
+  (net 7 /CH5)
+  (net 8 /CH6)
+  (net 9 /CH7)
+  (net 10 /CS0)
+  (net 11 /D2)
+  (net 12 /D3)
+  (net 13 /D5)
+  (net 14 /D6)
+  (net 15 /MISO)
+  (net 16 /MOSI)
+  (net 17 /SCK)
+  (net 18 /SSTRB)
+  (net 19 GND)
+  (net 20 N-000001)
+  (net 21 N-0000011)
+  (net 22 N-0000012)
+  (net 23 N-0000013)
+  (net 24 N-0000014)
+  (net 25 N-0000015)
+  (net 26 N-0000016)
+  (net 27 N-0000017)
+  (net 28 N-0000018)
+  (net 29 N-0000019)
+  (net 30 N-000002)
+  (net 31 N-0000020)
+  (net 32 N-0000022)
+  (net 33 N-0000024)
+  (net 34 N-0000026)
+  (net 35 N-0000027)
+  (net 36 N-0000028)
+  (net 37 N-0000029)
+  (net 38 N-000003)
+  (net 39 N-000004)
+  (net 40 N-000005)
+  (net 41 N-000007)
+  (net 42 N-000009)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.254)
+    (trace_width 0.508)
+    (via_dia 0.889)
+    (via_drill 0.635)
+    (uvia_dia 0.508)
+    (uvia_drill 0.127)
+    (add_net "")
+    (add_net /5V)
+    (add_net /CH0)
+    (add_net /CH1)
+    (add_net /CH2)
+    (add_net /CH3)
+    (add_net /CH4)
+    (add_net /CH5)
+    (add_net /CH6)
+    (add_net /CH7)
+    (add_net /CS0)
+    (add_net /D2)
+    (add_net /D3)
+    (add_net /D5)
+    (add_net /D6)
+    (add_net /MISO)
+    (add_net /MOSI)
+    (add_net /SCK)
+    (add_net /SSTRB)
+    (add_net GND)
+    (add_net N-000001)
+    (add_net N-0000011)
+    (add_net N-0000012)
+    (add_net N-0000013)
+    (add_net N-0000014)
+    (add_net N-0000015)
+    (add_net N-0000016)
+    (add_net N-0000017)
+    (add_net N-0000018)
+    (add_net N-0000019)
+    (add_net N-000002)
+    (add_net N-0000020)
+    (add_net N-0000022)
+    (add_net N-0000024)
+    (add_net N-0000026)
+    (add_net N-0000027)
+    (add_net N-0000028)
+    (add_net N-0000029)
+    (add_net N-000003)
+    (add_net N-000004)
+    (add_net N-000005)
+    (add_net N-000007)
+    (add_net N-000009)
+  )
+
+  (module ARDUINO_SHIELD (layer Front) (tedit 5053CA94) (tstamp 521801C8)
+    (at 114.902 133.8)
+    (path /4FFEFE94)
+    (fp_text reference SHIELD1 (at 22.89302 -3.49758) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text value ARDUINO_SHIELD (at 20.86102 -6.41858) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (pad AD5 thru_hole oval (at 63.5 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 28 N-0000018)
+    )
+    (pad AD4 thru_hole oval (at 60.96 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 27 N-0000017)
+    )
+    (pad AD3 thru_hole oval (at 58.42 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 25 N-0000015)
+    )
+    (pad AD0 thru_hole oval (at 50.8 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 22 N-0000012)
+    )
+    (pad AD1 thru_hole oval (at 53.34 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 23 N-0000013)
+    )
+    (pad AD2 thru_hole oval (at 55.88 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 24 N-0000014)
+    )
+    (pad V_IN thru_hole oval (at 45.72 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 38 N-000003)
+    )
+    (pad GND2 thru_hole oval (at 43.18 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 31 N-0000020)
+    )
+    (pad GND1 thru_hole oval (at 40.64 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+    (pad 3V3 thru_hole oval (at 35.56 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 26 N-0000016)
+    )
+    (pad RST thru_hole oval (at 33.02 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 29 N-0000019)
+    )
+    (pad 0 thru_hole oval (at 63.5 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 39 N-000004)
+    )
+    (pad 1 thru_hole oval (at 60.96 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 40 N-000005)
+    )
+    (pad 2 thru_hole oval (at 58.42 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 11 /D2)
+    )
+    (pad 3 thru_hole oval (at 55.88 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 12 /D3)
+    )
+    (pad 4 thru_hole oval (at 53.34 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 41 N-000007)
+    )
+    (pad 5 thru_hole oval (at 50.8 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 13 /D5)
+    )
+    (pad 6 thru_hole oval (at 48.26 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 14 /D6)
+    )
+    (pad 7 thru_hole oval (at 45.72 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 42 N-000009)
+    )
+    (pad 8 thru_hole oval (at 41.656 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 18 /SSTRB)
+    )
+    (pad 9 thru_hole oval (at 39.116 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 21 N-0000011)
+    )
+    (pad 10 thru_hole oval (at 36.576 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 10 /CS0)
+    )
+    (pad 11 thru_hole oval (at 34.036 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 16 /MOSI)
+    )
+    (pad 12 thru_hole oval (at 31.496 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 15 /MISO)
+    )
+    (pad 13 thru_hole oval (at 28.956 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 17 /SCK)
+    )
+    (pad GND3 thru_hole oval (at 26.416 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 20 N-000001)
+    )
+    (pad AREF thru_hole oval (at 23.876 -50.8 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 30 N-000002)
+    )
+    (pad 5V thru_hole oval (at 38.1 -2.54 90) (size 2.54 1.524) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 /5V)
+    )
+    (pad "" thru_hole circle (at 66.04 -7.62 90) (size 3.937 3.937) (drill 3.175)
+      (layers *.Cu *.Mask F.SilkS)
+    )
+    (pad "" thru_hole circle (at 66.04 -35.56 90) (size 3.937 3.937) (drill 3.175)
+      (layers *.Cu *.Mask F.SilkS)
+    )
+    (pad "" thru_hole circle (at 15.24 -50.8 90) (size 3.937 3.937) (drill 3.175)
+      (layers *.Cu *.Mask F.SilkS)
+    )
+    (pad "" thru_hole circle (at 13.97 -2.54 90) (size 3.937 3.937) (drill 3.175)
+      (layers *.Cu *.Mask F.SilkS)
+    )
+  )
+
+  (module DIP-24__300_ELL (layer Front) (tedit 52180508) (tstamp 52180135)
+    (at 158.5 107.112 180)
+    (descr "24 pins DIL package, elliptical pads")
+    (tags DIL)
+    (path /4D1E7C35)
+    (fp_text reference U8 (at 18.32 0.0518 180) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_text value MAX1270-PDIP (at -0.49 0.0118 180) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_line (start -16.51 -1.27) (end -15.24 -1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start -15.24 -1.27) (end -15.24 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start -15.24 1.27) (end -16.51 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start -16.51 1.27) (end -16.51 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start -16.51 -2.54) (end 16.51 -2.54) (layer F.SilkS) (width 0.381))
+    (fp_line (start 16.51 -2.54) (end 16.51 2.54) (layer F.SilkS) (width 0.381))
+    (fp_line (start 16.51 2.54) (end -16.51 2.54) (layer F.SilkS) (width 0.381))
+    (fp_line (start -16.51 2.54) (end -16.51 -2.54) (layer F.SilkS) (width 0.381))
+    (pad 1 thru_hole rect (at -13.97 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 /5V)
+    )
+    (pad 2 thru_hole oval (at -11.43 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+    (pad 3 thru_hole oval (at -8.89 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 32 N-0000022)
+    )
+    (pad 4 thru_hole oval (at -6.35 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+    (pad 5 thru_hole oval (at -3.81 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 17 /SCK)
+    )
+    (pad 6 thru_hole oval (at -1.27 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 10 /CS0)
+    )
+    (pad 7 thru_hole oval (at 1.27 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 16 /MOSI)
+    )
+    (pad 8 thru_hole oval (at 3.81 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 18 /SSTRB)
+    )
+    (pad 9 thru_hole oval (at 6.35 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 33 N-0000024)
+    )
+    (pad 10 thru_hole oval (at 8.89 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 15 /MISO)
+    )
+    (pad 11 thru_hole oval (at 11.43 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 /5V)
+    )
+    (pad 12 thru_hole oval (at 13.97 3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+    (pad 13 thru_hole oval (at 13.97 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 2 /CH0)
+    )
+    (pad 14 thru_hole oval (at 11.43 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 3 /CH1)
+    )
+    (pad 15 thru_hole oval (at 8.89 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 4 /CH2)
+    )
+    (pad 16 thru_hole oval (at 6.35 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 5 /CH3)
+    )
+    (pad 17 thru_hole oval (at 3.81 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 6 /CH4)
+    )
+    (pad 18 thru_hole oval (at 1.27 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 7 /CH5)
+    )
+    (pad 19 thru_hole oval (at -1.27 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 8 /CH6)
+    )
+    (pad 20 thru_hole oval (at -3.81 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 9 /CH7)
+    )
+    (pad 21 thru_hole oval (at -6.35 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 34 N-0000026)
+    )
+    (pad 22 thru_hole oval (at -8.89 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 35 N-0000027)
+    )
+    (pad 23 thru_hole oval (at -11.43 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 36 N-0000028)
+    )
+    (pad 24 thru_hole oval (at -13.97 -3.81 180) (size 1.5748 2.286) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 37 N-0000029)
+    )
+    (model dil/dil_24-w300.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module CONN_13 (layer Front) (tedit 521804BF) (tstamp 500451E5)
+    (at 192.639 107.124 90)
+    (path /4FFF3BBA)
+    (fp_text reference P1 (at -24.8055 -0.79868 90) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_text value CONN_13 (at 0 -5.10032 90) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_line (start 23.30196 -3.59918) (end -23.29942 -3.59918) (layer F.SilkS) (width 0.381))
+    (fp_line (start 23.29942 3.49758) (end -23.29942 3.49758) (layer F.SilkS) (width 0.381))
+    (fp_line (start -23.30196 -3.60172) (end -23.30196 3.39852) (layer F.SilkS) (width 0.381))
+    (fp_line (start 23.3045 -3.59918) (end 23.3045 3.50012) (layer F.SilkS) (width 0.381))
+    (pad 1 thru_hole oval (at -21.00326 0.00254 270) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 2 /CH0)
+    )
+    (pad 2 thru_hole oval (at -17.50568 0 270) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 3 /CH1)
+    )
+    (pad 3 thru_hole oval (at -13.99794 -0.00254 270) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 4 /CH2)
+    )
+    (pad 4 thru_hole oval (at -10.50036 0 270) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 5 /CH3)
+    )
+    (pad 5 thru_hole oval (at -7.00024 0 270) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 6 /CH4)
+    )
+    (pad 6 thru_hole oval (at -3.5052 0 270) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 7 /CH5)
+    )
+    (pad 7 thru_hole oval (at -0.00254 0 270) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 8 /CH6)
+    )
+    (pad 8 thru_hole oval (at 3.49758 -0.00254 90) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 9 /CH7)
+    )
+    (pad 9 thru_hole oval (at 6.9977 -0.00254 90) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 11 /D2)
+    )
+    (pad 10 thru_hole oval (at 10.5029 -0.00254 90) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 12 /D3)
+    )
+    (pad 12 thru_hole oval (at 17.49806 -0.00508 90) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 14 /D6)
+    )
+    (pad 11 thru_hole oval (at 13.99794 -0.00254 90) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 13 /D5)
+    )
+    (pad 13 thru_hole oval (at 20.99818 -0.00254 270) (size 1.651 2.54) (drill 0.89916)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+  )
+
+  (module C1_Big_Pad (layer Front) (tedit 5218085E) (tstamp 52186E4B)
+    (at 164.55 118.22 270)
+    (descr "Condensateur e = 1 pas")
+    (tags C)
+    (path /4D1E88E9)
+    (fp_text reference C3 (at 4.01 -0.08 270) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_text value 0.01uF (at 0 2.39 270) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_line (start -2.4892 -1.27) (end 2.54 -1.27) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 2.54 -1.27) (end 2.54 1.27) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 2.54 1.27) (end -2.54 1.27) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -2.54 1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -2.54 -0.635) (end -1.905 -1.27) (layer F.SilkS) (width 0.3048))
+    (pad 1 thru_hole circle (at -1.27 0 270) (size 1.651 1.651) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 34 N-0000026)
+    )
+    (pad 2 thru_hole circle (at 1.27 0 270) (size 1.651 1.651) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+    (model discret/capa_1_pas.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module C2_Big_Pad (layer Front) (tedit 521808BC) (tstamp 52186F19)
+    (at 170.15 118.24 270)
+    (descr "Condensateur = 2 pas")
+    (tags C)
+    (path /4D1E88FA)
+    (fp_text reference C1 (at 4.85 -0.05 270) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_text value 4.7uF (at -0.02 -2.16 270) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_line (start -3.556 -1.016) (end 3.556 -1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 3.556 -1.016) (end 3.556 1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 3.556 1.016) (end -3.556 1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -3.556 1.016) (end -3.556 -1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -3.556 -0.508) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048))
+    (pad 1 thru_hole circle (at -2.54 0 270) (size 1.651 1.651) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 36 N-0000028)
+    )
+    (pad 2 thru_hole circle (at 2.54 0 270) (size 1.651 1.651) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+    (model discret/capa_2pas_5x5mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module C2_Big_Pad (layer Front) (tedit 5218064A) (tstamp 52186FE7)
+    (at 174.96 94.34 90)
+    (descr "Condensateur = 2 pas")
+    (tags C)
+    (path /4D1E8852)
+    (fp_text reference C2 (at 0 0 90) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_text value 0.1uF (at 0 0 90) (layer F.SilkS) hide
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_line (start -3.556 -1.016) (end 3.556 -1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 3.556 -1.016) (end 3.556 1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 3.556 1.016) (end -3.556 1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -3.556 1.016) (end -3.556 -1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -3.556 -0.508) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048))
+    (pad 1 thru_hole circle (at -2.54 0 90) (size 1.651 1.651) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 /5V)
+    )
+    (pad 2 thru_hole circle (at 2.54 0 90) (size 1.651 1.651) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+    (model discret/capa_2pas_5x5mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module C2_Big_Pad (layer Front) (tedit 5218064A) (tstamp 52186FF2)
+    (at 169.47 94.34 90)
+    (descr "Condensateur = 2 pas")
+    (tags C)
+    (path /4D2273C2)
+    (fp_text reference C4 (at 0 0 90) (layer F.SilkS)
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_text value 4.7uF (at 0 0 90) (layer F.SilkS) hide
+      (effects (font (size 1.016 1.016) (thickness 0.2032)))
+    )
+    (fp_line (start -3.556 -1.016) (end 3.556 -1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 3.556 -1.016) (end 3.556 1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start 3.556 1.016) (end -3.556 1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -3.556 1.016) (end -3.556 -1.016) (layer F.SilkS) (width 0.3048))
+    (fp_line (start -3.556 -0.508) (end -3.048 -1.016) (layer F.SilkS) (width 0.3048))
+    (pad 1 thru_hole circle (at -2.54 0 90) (size 1.651 1.651) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 /5V)
+    )
+    (pad 2 thru_hole circle (at 2.54 0 90) (size 1.651 1.651) (drill 0.8128)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 19 GND)
+    )
+    (model discret/capa_2pas_5x5mm.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_line (start 196.1388 133.79958) (end 123.7488 133.79958) (angle 90) (layer Edge.Cuts) (width 0.381))
+  (gr_text D8 (at 156.7434 85.725 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D9 (at 154.2288 85.725 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D10 (at 151.511 86.2076 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D11 (at 148.9456 86.106 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D12 (at 146.4056 86.1314 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D13 (at 143.891 86.0806 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text RX (at 178.4604 85.7504 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text TX (at 175.9204 85.725 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D4 (at 168.3004 85.7504 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D7 (at 160.7566 85.7504 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text "MAX1270 Analog Input Sheild\nIO Rodeo Inc.  V0.2" (at 127.1778 107.696 90) (layer F.SilkS)
+    (effects (font (size 2.032 1.524) (thickness 0.3048)))
+  )
+  (gr_text AD5 (at 178.435 127.762 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text AD4 (at 175.895 127.762 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text AD3 (at 173.228 127.762 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text AD2 (at 170.815 127.762 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text AD1 (at 168.148 127.762 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text AD0 (at 165.608 127.762 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text V_IN (at 160.655 127.635 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text GND (at 158.242 127.762 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text GND (at 155.702 127.762 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text 5V (at 153.035 128.397 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text 3V3 (at 150.495 127.889 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text RST (at 147.955 128.016 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text AREF (at 138.8618 86.2584 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text GND (at 141.4272 86.106 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text SCK (at 143.891 89.5096 90) (layer F.SilkS)
+    (effects (font (size 1.016 0.762) (thickness 0.1524)))
+  )
+  (gr_text MISO (at 146.3802 89.4588 90) (layer F.SilkS)
+    (effects (font (size 1.016 0.762) (thickness 0.1524)))
+  )
+  (gr_text MOSI (at 149.0726 89.535 90) (layer F.SilkS)
+    (effects (font (size 1.016 0.762) (thickness 0.1524)))
+  )
+  (gr_text CS0 (at 151.5364 89.3572 90) (layer F.SilkS)
+    (effects (font (size 1.016 0.762) (thickness 0.1524)))
+  )
+  (gr_text SSTRB (at 156.8196 89.027 90) (layer F.SilkS)
+    (effects (font (size 1.016 0.762) (thickness 0.1524)))
+  )
+  (gr_text D6 (at 163.1696 85.7504 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D5 (at 165.735 85.7504 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D3 (at 170.9166 85.7504 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D2 (at 173.3804 85.7504 90) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text GND (at 186.944 86.106) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D6 (at 187.452 89.408) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
+  )
+  (gr_text D5 (at 187.452 93.091) (layer F.SilkS)
+    (effects (font (size 1.016 1.016) (thickness 0.1524)))
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