Commits

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Author Commit Message Labels Comments Date
iorodeo
Modified BOM to help mitigate lead time and part availability issues.
iorodeo
Added fab directory for version 1.3 of the design.
iorodeo
Added zipped archive of version 1.3 of the gerber files.
iorodeo
Made power and ground traces slightly fatter. Nudge a couple of other traces so that design passes drc. Created new gerber files.:
Cisco Zabala
generated xy files
Cisco Zabala
minor correction on bottom silkscreen
Cisco Zabala
Added BOM from Bitele
Cisco Zabala
Rerouted due to short on the back plane.
Cisco Zabala
re-routed the board without zones.
Cisco Zabala
added logo to the PCB
Cisco Zabala
renamed pcb folder
Cisco Zabala
finalized v1.0
Cisco Zabala
removing legacy files.
Cisco Zabala
Finished design of PCB.
Cisco Zabala
v1.0 done.
Cisco Zabala
board routed.
Cisco Zabala
temporarily adding RGB matrix kicad files
Cisco Zabala
adding old design files.
XZLab
First commit