Commits

iorodeo committed 50a72a4

Added programmer pcb for atmega328 four panel 20mm matrix design.

  • Participants
  • Parent commits 923d14f

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Files changed (15)

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/3X2_SHRD_HEADER.mod

+PCBNEW-LibModule-V1  Mon 23 Sep 2013 03:19:46 PM PDT
+# encoding utf-8
+Units mm
+$INDEX
+3X2_SHRD_HEADER
+$EndINDEX
+$MODULE 3X2_SHRD_HEADER
+Po 0 0 0 15 5240BE5A 00000000 ~~
+Li 3X2_SHRD_HEADER
+Sc 0
+AR 
+Op 0 0 0
+T0 0 -7.874 1.524 1.524 0 0.3048 N V 21 N "3X2_SHRD_HEADER"
+T1 5.19938 6.2992 1.524 1.524 0 0.3048 N V 21 N "VAL**"
+T2 2.54 3.556 1.27 1.27 0 0.254 N V 21 N "5"
+T2 2.54 -3.302 1.27 1.27 0 0.254 N V 21 N "6"
+DS -7.62 4.826 7.62 4.826 0.381 21
+DS -7.62 -4.826 7.62 -4.826 0.381 21
+DS 7.62 -4.826 7.62 4.826 0.381 21
+DS -7.62 4.826 -7.62 -4.826 0.381 21
+DS -4.36118 7.29996 -1.3589 7.29996 0.381 21
+T2 -2.54 -3.302 1.27 1.27 0 0.254 N V 21 N "2"
+DS -2.82448 5.48894 -4.34848 7.26694 0.381 21
+DS -1.30048 7.2644 -2.82448 5.4864 0.381 21
+$PAD
+Sh "1" R 1.778 1.778 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -2.54 1.27
+$EndPAD
+$PAD
+Sh "2" C 1.778 1.778 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -2.54 -1.27
+$EndPAD
+$PAD
+Sh "3" C 1.778 1.778 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 0 1.27
+$EndPAD
+$PAD
+Sh "4" C 1.778 1.778 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 0 -1.27
+$EndPAD
+$PAD
+Sh "5" C 1.778 1.778 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 2.54 1.27
+$EndPAD
+$PAD
+Sh "6" C 1.778 1.778 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 2.54 -1.27
+$EndPAD
+$EndMODULE 3X2_SHRD_HEADER
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/DCJACK_2PIN.mod

+PCBNEW-LibModule-V1  Thu 21 Jun 2012 04:30:35 PM PDT
+# encoding utf-8
+$INDEX
+DCJACK_2PIN
+$EndINDEX
+$MODULE DCJACK_2PIN
+Po 0 0 0 15 4CFD9C4C 4FE3AE85 ~~
+Li DCJACK_2PIN
+Sc 4FE3AE85
+AR 
+Op 0 0 0
+T0 2913 -2913 600 600 0 120 N V 21 N "DCJACK_2PIN"
+T1 3110 2677 600 600 0 120 N I 21 N "VAL**"
+DS 0 -1063 0 -1772 150 21
+DS 0 -1772 5433 -1772 150 21
+DS 5433 -1772 5433 1732 150 21
+DS 5433 1732 5433 1772 150 21
+DS 5433 1772 0 1772 150 21
+DS 0 1772 0 1063 150 21
+$PAD
+Sh "1" C 2000 2000 0 0 0
+Dr 1181 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 0 0
+$EndPAD
+$PAD
+Sh "2" C 1811 1811 0 0 0
+Dr 1024 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 2362 0
+$EndPAD
+$EndMODULE  DCJACK_2PIN
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/HEADER_TOP.mod

+PCBNEW-LibModule-V1  Fri 26 Jul 2013 11:21:22 AM PDT
+# encoding utf-8
+$INDEX
+HEADER_TOP
+$EndINDEX
+$MODULE HEADER_TOP
+Po 0 0 0 15 51F2BE17 00000000 ~~
+Li HEADER_TOP
+Sc 00000000
+AR HEADER_TOP
+Op 0 0 0
+T0 -2600 -1900 600 600 0 120 N V 21 N "HEADER_TOP"
+T1 3000 -1800 600 600 0 120 N V 21 N "VAL**"
+DS 6000 -3200 7500 -3200 150 21
+DS 7500 -3200 7500 -2900 150 21
+DS -6000 -3200 -7500 -3200 150 21
+DS -7500 -3200 -7500 -3000 150 21
+DS -6000 500 -7500 500 150 21
+DS -7500 500 -7500 -3000 150 21
+DS 6000 500 7500 500 150 21
+DS 7500 500 7500 -3000 150 21
+DS 6000 500 -6000 500 150 21
+DS -6000 -3200 6000 -3200 150 21
+$PAD
+Sh "1" R 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -7000 0
+$EndPAD
+$PAD
+Sh "2" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -6000 0
+$EndPAD
+$PAD
+Sh "3" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -5000 0
+$EndPAD
+$PAD
+Sh "4" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -4000 0
+$EndPAD
+$PAD
+Sh "5" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -3000 0
+$EndPAD
+$PAD
+Sh "6" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -2000 0
+$EndPAD
+$PAD
+Sh "7" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -1000 0
+$EndPAD
+$PAD
+Sh "8" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 0 0
+$EndPAD
+$PAD
+Sh "9" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 1000 0
+$EndPAD
+$PAD
+Sh "10" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 2000 0
+$EndPAD
+$PAD
+Sh "11" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 3000 0
+$EndPAD
+$PAD
+Sh "12" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 4000 0
+$EndPAD
+$PAD
+Sh "13" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 5000 0
+$EndPAD
+$PAD
+Sh "14" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 6000 0
+$EndPAD
+$PAD
+Sh "15" C 600 600 0 0 0
+Dr 400 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 7000 0
+$EndPAD
+$EndMODULE  HEADER_TOP
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/conn15.lib

+EESchema-LIBRARY Version 2.3  Date: Mon 19 Aug 2013 05:15:49 PM PDT
+#encoding utf-8
+#
+# CONN15
+#
+DEF CONN15 P 0 40 Y Y 1 F N
+F0 "P" -700 250 60 H V C CNN
+F1 "CONN15" 550 250 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -750 200 750 0 0 1 0 N
+X ~ 1 -700 -200 200 U 50 50 1 1 P
+X ~ 2 -600 -200 200 U 50 50 1 1 P
+X ~ 3 -500 -200 200 U 50 50 1 1 P
+X ~ 4 -400 -200 200 U 50 50 1 1 P
+X ~ 5 -300 -200 200 U 50 50 1 1 P
+X ~ 6 -200 -200 200 U 50 50 1 1 P
+X ~ 7 -100 -200 200 U 50 50 1 1 P
+X ~ 8 0 -200 200 U 50 50 1 1 P
+X ~ 9 100 -200 200 U 50 50 1 1 P
+X ~ 10 200 -200 200 U 50 50 1 1 P
+X ~ 11 300 -200 200 U 50 50 1 1 P
+X ~ 12 400 -200 200 U 50 50 1 1 I
+X ~ 13 500 -200 200 U 50 50 1 1 P
+X ~ 14 600 -200 200 U 50 50 1 1 P
+X ~ 15 700 -200 200 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer-cache.lib

+EESchema-LIBRARY Version 2.3  Date: Mon 23 Sep 2013 03:39:41 PM PDT
+#encoding utf-8
+#
+# +5V
+#
+DEF +5V #PWR 0 40 Y Y 1 F P
+F0 "#PWR" 0 90 20 H I C CNN
+F1 "+5V" 0 90 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+X +5V 1 0 0 0 U 20 20 0 0 W N
+C 0 50 20 0 1 0 N
+P 4 0 1 0  0 0  0 30  0 30  0 30 N
+ENDDRAW
+ENDDEF
+#
+# CONN15
+#
+DEF CONN15 P 0 40 Y Y 1 F N
+F0 "P" -700 250 60 H V C CNN
+F1 "CONN15" 550 250 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -750 200 750 0 0 1 0 N
+X ~ 1 -700 -200 200 U 50 50 1 1 P
+X ~ 2 -600 -200 200 U 50 50 1 1 P
+X ~ 3 -500 -200 200 U 50 50 1 1 P
+X ~ 4 -400 -200 200 U 50 50 1 1 P
+X ~ 5 -300 -200 200 U 50 50 1 1 P
+X ~ 6 -200 -200 200 U 50 50 1 1 P
+X ~ 7 -100 -200 200 U 50 50 1 1 P
+X ~ 8 0 -200 200 U 50 50 1 1 P
+X ~ 9 100 -200 200 U 50 50 1 1 P
+X ~ 10 200 -200 200 U 50 50 1 1 P
+X ~ 11 300 -200 200 U 50 50 1 1 P
+X ~ 12 400 -200 200 U 50 50 1 1 I
+X ~ 13 500 -200 200 U 50 50 1 1 P
+X ~ 14 600 -200 200 U 50 50 1 1 P
+X ~ 15 700 -200 200 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# CONN_2
+#
+DEF CONN_2 P 0 40 Y N 1 F N
+F0 "P" -50 0 40 V V C CNN
+F1 "CONN_2" 50 0 40 V V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -100 150 100 -150 0 1 0 N
+X P1 1 -350 100 250 R 60 60 1 1 P I
+X PM 2 -350 -100 250 R 60 60 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# CONN_3X2
+#
+DEF CONN_3X2 P 0 40 Y N 1 F N
+F0 "P" 0 250 50 H V C CNN
+F1 "CONN_3X2" 0 50 40 V V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -100 200 100 -100 0 1 0 N
+X 1 1 -400 150 300 R 60 60 1 1 P I
+X 2 2 400 150 300 L 60 60 1 1 P I
+X 3 3 -400 50 300 R 60 60 1 1 P I
+X 4 4 400 50 300 L 60 60 1 1 P I
+X 5 5 -400 -50 300 R 60 60 1 1 P I
+X 6 6 400 -50 300 L 60 60 1 1 P I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 30 H I C CNN
+F1 "PWR_FLAG" 0 180 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
+ENDDRAW
+ENDDEF
+#
+#End Library

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.bak

+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:conn15
+EELAYER 24 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CONN15 P3
+U 1 1 5240B882
+P 6000 1950
+F 0 "P3" H 5300 2200 60  0000 C CNN
+F 1 "CONN15" H 6550 2200 60  0000 C CNN
+F 2 "" H 6000 1950 60  0000 C CNN
+F 3 "" H 6000 1950 60  0000 C CNN
+	1    6000 1950
+	0    1    1    0   
+$EndComp
+$Comp
+L CONN_2 P1
+U 1 1 5240B8CC
+P 1150 1300
+F 0 "P1" V 1100 1300 40  0000 C CNN
+F 1 "CONN_2" V 1200 1300 40  0000 C CNN
+F 2 "" H 1150 1300 60  0000 C CNN
+F 3 "" H 1150 1300 60  0000 C CNN
+	1    1150 1300
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	1500 1400 1700 1400
+Wire Wire Line
+	1700 1400 1700 1600
+Wire Wire Line
+	1500 1200 1700 1200
+Wire Wire Line
+	1700 1200 1700 1000
+$Comp
+L GND #PWR01
+U 1 1 5240B8EF
+P 1700 1600
+F 0 "#PWR01" H 1700 1600 30  0001 C CNN
+F 1 "GND" H 1700 1530 30  0001 C CNN
+F 2 "" H 1700 1600 60  0000 C CNN
+F 3 "" H 1700 1600 60  0000 C CNN
+	1    1700 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L +5V #PWR02
+U 1 1 5240B90B
+P 1700 1000
+F 0 "#PWR02" H 1700 1090 20  0001 C CNN
+F 1 "+5V" H 1700 1090 30  0000 C CNN
+F 2 "" H 1700 1000 60  0000 C CNN
+F 3 "" H 1700 1000 60  0000 C CNN
+	1    1700 1000
+	1    0    0    -1  
+$EndComp
+$Comp
+L +5V #PWR03
+U 1 1 5240B91A
+P 5150 1100
+F 0 "#PWR03" H 5150 1190 20  0001 C CNN
+F 1 "+5V" H 5150 1190 30  0000 C CNN
+F 2 "" H 5150 1100 60  0000 C CNN
+F 3 "" H 5150 1100 60  0000 C CNN
+	1    5150 1100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5800 1450 5650 1450
+Wire Wire Line
+	5800 1550 5650 1550
+Text Label 5650 1550 2    60   ~ 0
+SCK
+Wire Wire Line
+	5800 1650 5650 1650
+Text Label 5650 1650 2    60   ~ 0
+MOSI
+Wire Wire Line
+	5800 1750 5650 1750
+Text Label 5650 1750 2    60   ~ 0
+MISO
+$Comp
+L GND #PWR04
+U 1 1 5240B9BF
+P 5150 1400
+F 0 "#PWR04" H 5150 1400 30  0001 C CNN
+F 1 "GND" H 5150 1330 30  0001 C CNN
+F 2 "" H 5150 1400 60  0000 C CNN
+F 3 "" H 5150 1400 60  0000 C CNN
+	1    5150 1400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5800 1350 5150 1350
+Wire Wire Line
+	5150 1350 5150 1400
+Wire Wire Line
+	5800 1250 5150 1250
+Wire Wire Line
+	5150 1250 5150 1100
+$Comp
+L CONN_3X2 P2
+U 1 1 5240BA0F
+P 3500 1400
+F 0 "P2" H 3500 1650 50  0000 C CNN
+F 1 "CONN_3X2" V 3500 1450 40  0000 C CNN
+F 2 "" H 3500 1400 60  0000 C CNN
+F 3 "" H 3500 1400 60  0000 C CNN
+	1    3500 1400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3100 1250 2900 1250
+Wire Wire Line
+	3100 1350 2900 1350
+Wire Wire Line
+	3100 1450 2900 1450
+Wire Wire Line
+	3900 1250 4100 1250
+Wire Wire Line
+	3900 1350 4100 1350
+Wire Wire Line
+	3900 1450 4100 1450
+Text Label 2900 1250 2    60   ~ 0
+MISO
+Text Label 2900 1350 2    60   ~ 0
+SCK
+Text Label 2900 1450 2    60   ~ 0
+~RST
+Text Label 4100 1350 0    60   ~ 0
+MOSI
+Wire Wire Line
+	4100 1450 4100 1600
+Wire Wire Line
+	4100 1250 4100 1100
+$Comp
+L +5V #PWR05
+U 1 1 5240BAB5
+P 4100 1100
+F 0 "#PWR05" H 4100 1190 20  0001 C CNN
+F 1 "+5V" H 4100 1190 30  0000 C CNN
+F 2 "" H 4100 1100 60  0000 C CNN
+F 3 "" H 4100 1100 60  0000 C CNN
+	1    4100 1100
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR06
+U 1 1 5240BAC4
+P 4100 1600
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+F 2 "" H 4100 1600 60  0000 C CNN
+F 3 "" H 4100 1600 60  0000 C CNN
+	1    4100 1600
+	1    0    0    -1  
+$EndComp
+Text Notes 3100 1800 0    60   ~ 0
+AVRISP HEADER
+Text Notes 1100 1850 0    60   ~ 0
+5V POWER 
+Text Notes 5350 2950 0    60   ~ 0
+COMM PANEL PROGRAMMER
+NoConn ~ 5800 1850
+NoConn ~ 5800 1950
+NoConn ~ 5800 2050
+NoConn ~ 5800 2150
+NoConn ~ 5800 2250
+NoConn ~ 5800 2350
+NoConn ~ 5800 2450
+NoConn ~ 5800 2550
+NoConn ~ 5800 2650
+NoConn ~ 2000 1650
+Text Label 5650 1450 2    60   ~ 0
+~RST
+$Comp
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+P 7350 950
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+F 2 "" H 7350 950 60  0000 C CNN
+F 3 "" H 7350 950 60  0000 C CNN
+	1    7350 950 
+	1    0    0    -1  
+$EndComp
+$Comp
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+P 7800 850
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+F 1 "+5V" H 7800 940 30  0000 C CNN
+F 2 "" H 7800 850 60  0000 C CNN
+F 3 "" H 7800 850 60  0000 C CNN
+	1    7800 850 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7350 950  7350 1050
+Wire Wire Line
+	7350 1050 7800 1050
+Wire Wire Line
+	7800 1050 7800 850 
+$Comp
+L GND #PWR09
+U 1 1 5240BC2F
+P 7000 1150
+F 0 "#PWR09" H 7000 1150 30  0001 C CNN
+F 1 "GND" H 7000 1080 30  0001 C CNN
+F 2 "" H 7000 1150 60  0000 C CNN
+F 3 "" H 7000 1150 60  0000 C CNN
+	1    7000 1150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG010
+U 1 1 5240BC44
+P 7000 950
+F 0 "#FLG010" H 7000 1045 30  0001 C CNN
+F 1 "PWR_FLAG" H 7000 1130 30  0000 C CNN
+F 2 "" H 7000 950 60  0000 C CNN
+F 3 "" H 7000 950 60  0000 C CNN
+	1    7000 950 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7000 950  7000 1150
+$EndSCHEMATC

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.cmp

+Cmp-Mod V01 Created by CvPcb (2013-mar-13)-testing date = Mon 23 Sep 2013 03:21:17 PM PDT
+
+BeginCmp
+TimeStamp = /5240B8CC;
+Reference = P1;
+ValeurCmp = CONN_2;
+IdModule  = DCJACK_2PIN;
+EndCmp
+
+BeginCmp
+TimeStamp = /5240BA0F;
+Reference = P2;
+ValeurCmp = CONN_3X2;
+IdModule  = 3X2_SHRD_HEADER;
+EndCmp
+
+BeginCmp
+TimeStamp = /5240B882;
+Reference = P3;
+ValeurCmp = CONN15;
+IdModule  = HEADER_TOP;
+EndCmp
+
+EndListe

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.dsn

+(pcb /home/wbd/work/iorodeo/products/panels_g4_hardware/atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.dsn
+  (parser
+    (string_quote ")
+    (space_in_quoted_tokens on)
+    (host_cad "KiCad's Pcbnew")
+    (host_version "(2013-mar-13)-testing")
+  )
+  (resolution um 10)
+  (unit um)
+  (structure
+    (layer F.Cu
+      (type signal)
+      (property
+        (index 0)
+      )
+    )
+    (layer B.Cu
+      (type signal)
+      (property
+        (index 1)
+      )
+    )
+    (boundary
+      (path pcb 0  90000 -90000  50000 -90000  50000 -50000  90000 -50000
+            90000 -90000)
+    )
+    (via "Via[0-1]_889:635_um" "Via[0-1]_889:0_um")
+    (rule
+      (width 635)
+      (clearance 254.1)
+      (clearance 254.1 (type default_smd))
+      (clearance 63.5 (type smd_smd))
+    )
+  )
+  (placement
+    (component DCJACK_2PIN
+      (place P1 56050 -76200 front 270 (PN CONN_2))
+    )
+    (component 3X2_SHRD_HEADER
+      (place P2 77300 -73400 front 180 (PN CONN_3X2))
+    )
+    (component HEADER_TOP
+      (place P3 70000 -58200 front 0 (PN CONN15))
+    )
+  )
+  (library
+    (image DCJACK_2PIN
+      (outline (path signal 381  0 2700.02  0 4500.88))
+      (outline (path signal 381  0 4500.88  13799.8 4500.88))
+      (outline (path signal 381  13799.8 4500.88  13799.8 -4399.28))
+      (outline (path signal 381  13799.8 -4399.28  13799.8 -4500.88))
+      (outline (path signal 381  13799.8 -4500.88  0 -4500.88))
+      (outline (path signal 381  0 -4500.88  0 -2700.02))
+      (pin Round[A]Pad_5080_um 1 0 0)
+      (pin Round[A]Pad_4599.94_um 2 5999.48 0)
+    )
+    (image 3X2_SHRD_HEADER
+      (outline (path signal 381  -7620 -4826  7620 -4826))
+      (outline (path signal 381  -7620 4826  7620 4826))
+      (outline (path signal 381  7620 4826  7620 -4826))
+      (outline (path signal 381  -7620 -4826  -7620 4826))
+      (outline (path signal 381  -4361.18 -7299.96  -1358.9 -7299.96))
+      (outline (path signal 381  -2824.48 -5488.94  -4348.48 -7266.94))
+      (outline (path signal 381  -1300.48 -7264.4  -2824.48 -5486.4))
+      (pin Rect[A]Pad_1778x1778_um 1 -2540 -1270)
+      (pin Round[A]Pad_1778_um 2 -2540 1270)
+      (pin Round[A]Pad_1778_um 3 0 -1270)
+      (pin Round[A]Pad_1778_um 4 0 1270)
+      (pin Round[A]Pad_1778_um 5 2540 -1270)
+      (pin Round[A]Pad_1778_um 6 2540 1270)
+    )
+    (image HEADER_TOP
+      (outline (path signal 381  15240 8128  19050 8128))
+      (outline (path signal 381  19050 8128  19050 7366))
+      (outline (path signal 381  -15240 8128  -19050 8128))
+      (outline (path signal 381  -19050 8128  -19050 7620))
+      (outline (path signal 381  -15240 -1270  -19050 -1270))
+      (outline (path signal 381  -19050 -1270  -19050 7620))
+      (outline (path signal 381  15240 -1270  19050 -1270))
+      (outline (path signal 381  19050 -1270  19050 7620))
+      (outline (path signal 381  15240 -1270  -15240 -1270))
+      (outline (path signal 381  -15240 8128  15240 8128))
+      (pin Rect[A]Pad_1524x1524_um 1 -17780 0)
+      (pin Round[A]Pad_1524_um 2 -15240 0)
+      (pin Round[A]Pad_1524_um 3 -12700 0)
+      (pin Round[A]Pad_1524_um 4 -10160 0)
+      (pin Round[A]Pad_1524_um 5 -7620 0)
+      (pin Round[A]Pad_1524_um 6 -5080 0)
+      (pin Round[A]Pad_1524_um 7 -2540 0)
+      (pin Round[A]Pad_1524_um 8 0 0)
+      (pin Round[A]Pad_1524_um 9 2540 0)
+      (pin Round[A]Pad_1524_um 10 5080 0)
+      (pin Round[A]Pad_1524_um 11 7620 0)
+      (pin Round[A]Pad_1524_um 12 10160 0)
+      (pin Round[A]Pad_1524_um 13 12700 0)
+      (pin Round[A]Pad_1524_um 14 15240 0)
+      (pin Round[A]Pad_1524_um 15 17780 0)
+    )
+    (padstack Round[A]Pad_1524_um
+      (shape (circle F.Cu 1524))
+      (shape (circle B.Cu 1524))
+      (attach off)
+    )
+    (padstack Round[A]Pad_1778_um
+      (shape (circle F.Cu 1778))
+      (shape (circle B.Cu 1778))
+      (attach off)
+    )
+    (padstack Round[A]Pad_4599.94_um
+      (shape (circle F.Cu 4599.94))
+      (shape (circle B.Cu 4599.94))
+      (attach off)
+    )
+    (padstack Round[A]Pad_5080_um
+      (shape (circle F.Cu 5080))
+      (shape (circle B.Cu 5080))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_1524x1524_um
+      (shape (rect F.Cu -762 -762 762 762))
+      (shape (rect B.Cu -762 -762 762 762))
+      (attach off)
+    )
+    (padstack Rect[A]Pad_1778x1778_um
+      (shape (rect F.Cu -889 -889 889 889))
+      (shape (rect B.Cu -889 -889 889 889))
+      (attach off)
+    )
+    (padstack "Via[0-1]_889:635_um"
+      (shape (circle F.Cu 889))
+      (shape (circle B.Cu 889))
+      (attach off)
+    )
+    (padstack "Via[0-1]_889:0_um"
+      (shape (circle F.Cu 889))
+      (shape (circle B.Cu 889))
+      (attach off)
+    )
+  )
+  (network
+    (net +5V
+      (pins P1-2 P2-2 P3-1)
+    )
+    (net /MISO
+      (pins P2-1 P3-6)
+    )
+    (net /MOSI
+      (pins P2-4 P3-5)
+    )
+    (net /SCK
+      (pins P2-3 P3-4)
+    )
+    (net /~RST
+      (pins P2-5 P3-3)
+    )
+    (net GND
+      (pins P1-1 P2-6 P3-2)
+    )
+    (net "N-0000010"
+      (pins P3-13)
+    )
+    (net "N-0000011"
+      (pins P3-12)
+    )
+    (net "N-0000012"
+      (pins P3-11)
+    )
+    (net "N-0000013"
+      (pins P3-10)
+    )
+    (net "N-0000014"
+      (pins P3-9)
+    )
+    (net "N-0000015"
+      (pins P3-8)
+    )
+    (net "N-0000016"
+      (pins P3-7)
+    )
+    (net "N-000008"
+      (pins P3-15)
+    )
+    (net "N-000009"
+      (pins P3-14)
+    )
+    (class kicad_default "" +5V /MISO /MOSI /SCK /~RST GND "N-0000010" "N-0000011"
+      "N-0000012" "N-0000013" "N-0000014" "N-0000015" "N-0000016" "N-000008"
+      "N-000009"
+      (circuit
+        (use_via Via[0-1]_889:635_um)
+      )
+      (rule
+        (width 635)
+        (clearance 254.1)
+      )
+    )
+  )
+  (wiring
+  )
+)

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.kicad_pcb

+(kicad_pcb (version 3) (host pcbnew "(2013-mar-13)-testing")
+
+  (general
+    (links 8)
+    (no_connects 0)
+    (area 49.949999 49.949999 90.050001 90.050001)
+    (thickness 1.6)
+    (drawings 6)
+    (tracks 20)
+    (zones 0)
+    (modules 3)
+    (nets 16)
+  )
+
+  (page A4)
+  (layers
+    (15 F.Cu signal)
+    (0 B.Cu signal)
+    (16 B.Adhes user)
+    (17 F.Adhes user)
+    (18 B.Paste user)
+    (19 F.Paste user)
+    (20 B.SilkS user)
+    (21 F.SilkS user)
+    (22 B.Mask user)
+    (23 F.Mask user)
+    (24 Dwgs.User user)
+    (25 Cmts.User user)
+    (26 Eco1.User user)
+    (27 Eco2.User user)
+    (28 Edge.Cuts user)
+  )
+
+  (setup
+    (last_trace_width 0.635)
+    (trace_clearance 0.254)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.254)
+    (segment_width 0.2)
+    (edge_width 0.1)
+    (via_size 0.889)
+    (via_drill 0.635)
+    (via_min_size 0.889)
+    (via_min_drill 0.508)
+    (uvia_size 0.508)
+    (uvia_drill 0.127)
+    (uvias_allowed no)
+    (uvia_min_size 0.508)
+    (uvia_min_drill 0.127)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.5 1.5)
+    (pad_drill 0.6)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 3178497)
+      (usegerberextensions true)
+      (excludeedgelayer true)
+      (linewidth 0.150000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15)
+      (hpglpenoverlay 2)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotothertext true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 +5V)
+  (net 2 /MISO)
+  (net 3 /MOSI)
+  (net 4 /SCK)
+  (net 5 /~RST)
+  (net 6 GND)
+  (net 7 N-0000010)
+  (net 8 N-0000011)
+  (net 9 N-0000012)
+  (net 10 N-0000013)
+  (net 11 N-0000014)
+  (net 12 N-0000015)
+  (net 13 N-0000016)
+  (net 14 N-000008)
+  (net 15 N-000009)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.254)
+    (trace_width 0.635)
+    (via_dia 0.889)
+    (via_drill 0.635)
+    (uvia_dia 0.508)
+    (uvia_drill 0.127)
+    (add_net "")
+    (add_net +5V)
+    (add_net /MISO)
+    (add_net /MOSI)
+    (add_net /SCK)
+    (add_net /~RST)
+    (add_net GND)
+    (add_net N-0000010)
+    (add_net N-0000011)
+    (add_net N-0000012)
+    (add_net N-0000013)
+    (add_net N-0000014)
+    (add_net N-0000015)
+    (add_net N-0000016)
+    (add_net N-000008)
+    (add_net N-000009)
+  )
+
+  (module DCJACK_2PIN (layer F.Cu) (tedit 5240C1EC) (tstamp 5240C0DC)
+    (at 56.05 76.2 270)
+    (path /5240B8CC)
+    (fp_text reference P1 (at -2.05 3.7 360) (layer F.SilkS)
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text value CONN_2 (at 7.8994 6.79958 270) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_line (start 0 -2.70002) (end 0 -4.50088) (layer F.SilkS) (width 0.381))
+    (fp_line (start 0 -4.50088) (end 13.79982 -4.50088) (layer F.SilkS) (width 0.381))
+    (fp_line (start 13.79982 -4.50088) (end 13.79982 4.39928) (layer F.SilkS) (width 0.381))
+    (fp_line (start 13.79982 4.39928) (end 13.79982 4.50088) (layer F.SilkS) (width 0.381))
+    (fp_line (start 13.79982 4.50088) (end 0 4.50088) (layer F.SilkS) (width 0.381))
+    (fp_line (start 0 4.50088) (end 0 2.70002) (layer F.SilkS) (width 0.381))
+    (pad 1 thru_hole circle (at 0 0 270) (size 5.08 5.08) (drill 2.99974)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 6 GND)
+    )
+    (pad 2 thru_hole circle (at 5.99948 0 270) (size 4.59994 4.59994) (drill 2.60096)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 +5V)
+    )
+  )
+
+  (module 3X2_SHRD_HEADER (layer F.Cu) (tedit 5240C1F1) (tstamp 5240C0F0)
+    (at 77.3 73.4 180)
+    (path /5240BA0F)
+    (fp_text reference P2 (at 9.6 4.1 180) (layer F.SilkS)
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text value CONN_3X2 (at 5.19938 6.2992 180) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text user 5 (at 2.54 3.556 180) (layer F.SilkS)
+      (effects (font (size 1.27 1.27) (thickness 0.254)))
+    )
+    (fp_text user 6 (at 2.54 -3.302 180) (layer F.SilkS)
+      (effects (font (size 1.27 1.27) (thickness 0.254)))
+    )
+    (fp_line (start -7.62 4.826) (end 7.62 4.826) (layer F.SilkS) (width 0.381))
+    (fp_line (start -7.62 -4.826) (end 7.62 -4.826) (layer F.SilkS) (width 0.381))
+    (fp_line (start 7.62 -4.826) (end 7.62 4.826) (layer F.SilkS) (width 0.381))
+    (fp_line (start -7.62 4.826) (end -7.62 -4.826) (layer F.SilkS) (width 0.381))
+    (fp_line (start -4.36118 7.29996) (end -1.3589 7.29996) (layer F.SilkS) (width 0.381))
+    (fp_text user 2 (at -2.54 -3.302 180) (layer F.SilkS)
+      (effects (font (size 1.27 1.27) (thickness 0.254)))
+    )
+    (fp_line (start -2.82448 5.48894) (end -4.34848 7.26694) (layer F.SilkS) (width 0.381))
+    (fp_line (start -1.30048 7.2644) (end -2.82448 5.4864) (layer F.SilkS) (width 0.381))
+    (pad 1 thru_hole rect (at -2.54 1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 2 /MISO)
+    )
+    (pad 2 thru_hole circle (at -2.54 -1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 +5V)
+    )
+    (pad 3 thru_hole circle (at 0 1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 4 /SCK)
+    )
+    (pad 4 thru_hole circle (at 0 -1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 3 /MOSI)
+    )
+    (pad 5 thru_hole circle (at 2.54 1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 5 /~RST)
+    )
+    (pad 6 thru_hole circle (at 2.54 -1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 6 GND)
+    )
+  )
+
+  (module HEADER_TOP (layer F.Cu) (tedit 5240C200) (tstamp 5240C10D)
+    (at 70 58.2)
+    (path /5240B882)
+    (fp_text reference P3 (at -17.8 2.85) (layer F.SilkS)
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text value CONN15 (at 7.62 -4.572) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_line (start 15.24 -8.128) (end 19.05 -8.128) (layer F.SilkS) (width 0.381))
+    (fp_line (start 19.05 -8.128) (end 19.05 -7.366) (layer F.SilkS) (width 0.381))
+    (fp_line (start -15.24 -8.128) (end -19.05 -8.128) (layer F.SilkS) (width 0.381))
+    (fp_line (start -19.05 -8.128) (end -19.05 -7.62) (layer F.SilkS) (width 0.381))
+    (fp_line (start -15.24 1.27) (end -19.05 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start -19.05 1.27) (end -19.05 -7.62) (layer F.SilkS) (width 0.381))
+    (fp_line (start 15.24 1.27) (end 19.05 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start 19.05 1.27) (end 19.05 -7.62) (layer F.SilkS) (width 0.381))
+    (fp_line (start 15.24 1.27) (end -15.24 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start -15.24 -8.128) (end 15.24 -8.128) (layer F.SilkS) (width 0.381))
+    (pad 1 thru_hole rect (at -17.78 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 +5V)
+    )
+    (pad 2 thru_hole circle (at -15.24 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 6 GND)
+    )
+    (pad 3 thru_hole circle (at -12.7 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 5 /~RST)
+    )
+    (pad 4 thru_hole circle (at -10.16 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 4 /SCK)
+    )
+    (pad 5 thru_hole circle (at -7.62 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 3 /MOSI)
+    )
+    (pad 6 thru_hole circle (at -5.08 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 2 /MISO)
+    )
+    (pad 7 thru_hole circle (at -2.54 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 13 N-0000016)
+    )
+    (pad 8 thru_hole circle (at 0 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 12 N-0000015)
+    )
+    (pad 9 thru_hole circle (at 2.54 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 11 N-0000014)
+    )
+    (pad 10 thru_hole circle (at 5.08 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 10 N-0000013)
+    )
+    (pad 11 thru_hole circle (at 7.62 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 9 N-0000012)
+    )
+    (pad 12 thru_hole circle (at 10.16 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 8 N-0000011)
+    )
+    (pad 13 thru_hole circle (at 12.7 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 7 N-0000010)
+    )
+    (pad 14 thru_hole circle (at 15.24 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 15 N-000009)
+    )
+    (pad 15 thru_hole circle (at 17.78 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 14 N-000008)
+    )
+  )
+
+  (gr_text www.iorodeo.com (at 79.75 87.85) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.254)))
+  )
+  (gr_text AVRISP (at 77.95 79.9) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.254)))
+  )
+  (gr_line (start 90 90) (end 90 50) (angle 90) (layer Edge.Cuts) (width 0.3))
+  (gr_line (start 50 90) (end 90 90) (angle 90) (layer Edge.Cuts) (width 0.3))
+  (gr_line (start 50 50) (end 50 90) (angle 90) (layer Edge.Cuts) (width 0.3))
+  (gr_line (start 90 50) (end 50 50) (angle 90) (layer Edge.Cuts) (width 0.3))
+
+  (segment (start 52.22 78.3695) (end 56.05 82.1995) (width 0.635) (layer B.Cu) (net 1))
+  (segment (start 52.22 58.2) (end 52.22 78.3695) (width 0.635) (layer B.Cu) (net 1))
+  (segment (start 72.3105 82.1995) (end 56.05 82.1995) (width 0.635) (layer F.Cu) (net 1))
+  (segment (start 79.84 74.67) (end 72.3105 82.1995) (width 0.635) (layer F.Cu) (net 1))
+  (segment (start 74.0243 66.3143) (end 79.84 72.13) (width 0.635) (layer F.Cu) (net 2))
+  (segment (start 73.0343 66.3143) (end 74.0243 66.3143) (width 0.635) (layer F.Cu) (net 2))
+  (segment (start 64.92 58.2) (end 73.0343 66.3143) (width 0.635) (layer F.Cu) (net 2))
+  (segment (start 75.8091 76.1609) (end 77.3 74.67) (width 0.635) (layer B.Cu) (net 3))
+  (segment (start 74.1848 76.1609) (end 75.8091 76.1609) (width 0.635) (layer B.Cu) (net 3))
+  (segment (start 62.38 64.3561) (end 74.1848 76.1609) (width 0.635) (layer B.Cu) (net 3))
+  (segment (start 62.38 58.2) (end 62.38 64.3561) (width 0.635) (layer B.Cu) (net 3))
+  (segment (start 70.9527 69.3127) (end 59.84 58.2) (width 0.635) (layer F.Cu) (net 4))
+  (segment (start 74.4827 69.3127) (end 70.9527 69.3127) (width 0.635) (layer F.Cu) (net 4))
+  (segment (start 77.3 72.13) (end 74.4827 69.3127) (width 0.635) (layer F.Cu) (net 4))
+  (segment (start 71.23 72.13) (end 74.76 72.13) (width 0.635) (layer F.Cu) (net 5))
+  (segment (start 57.3 58.2) (end 71.23 72.13) (width 0.635) (layer F.Cu) (net 5))
+  (segment (start 54.76 71.85) (end 57.58 74.67) (width 0.635) (layer F.Cu) (net 6))
+  (segment (start 54.76 58.2) (end 54.76 71.85) (width 0.635) (layer F.Cu) (net 6))
+  (segment (start 74.76 74.67) (end 57.58 74.67) (width 0.635) (layer F.Cu) (net 6))
+  (segment (start 57.58 74.67) (end 56.05 76.2) (width 0.635) (layer F.Cu) (net 6))
+
+)

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.kicad_pcb-bak

+(kicad_pcb (version 3) (host pcbnew "(2013-mar-13)-testing")
+
+  (general
+    (links 8)
+    (no_connects 8)
+    (area 49.949999 49.949999 90.050001 90.050001)
+    (thickness 1.6)
+    (drawings 6)
+    (tracks 0)
+    (zones 0)
+    (modules 3)
+    (nets 16)
+  )
+
+  (page A4)
+  (layers
+    (15 F.Cu signal)
+    (0 B.Cu signal)
+    (16 B.Adhes user)
+    (17 F.Adhes user)
+    (18 B.Paste user)
+    (19 F.Paste user)
+    (20 B.SilkS user)
+    (21 F.SilkS user)
+    (22 B.Mask user)
+    (23 F.Mask user)
+    (24 Dwgs.User user)
+    (25 Cmts.User user)
+    (26 Eco1.User user)
+    (27 Eco2.User user)
+    (28 Edge.Cuts user)
+  )
+
+  (setup
+    (last_trace_width 0.635)
+    (trace_clearance 0.254)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.254)
+    (segment_width 0.2)
+    (edge_width 0.1)
+    (via_size 0.889)
+    (via_drill 0.635)
+    (via_min_size 0.889)
+    (via_min_drill 0.508)
+    (uvia_size 0.508)
+    (uvia_drill 0.127)
+    (uvias_allowed no)
+    (uvia_min_size 0.508)
+    (uvia_min_drill 0.127)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.15)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.5 1.5)
+    (pad_drill 0.6)
+    (pad_to_mask_clearance 0)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFFFF7F)
+    (pcbplotparams
+      (layerselection 3178497)
+      (usegerberextensions true)
+      (excludeedgelayer true)
+      (linewidth 0.150000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15)
+      (hpglpenoverlay 2)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotothertext true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 1)
+      (scaleselection 1)
+      (outputdirectory ""))
+  )
+
+  (net 0 "")
+  (net 1 +5V)
+  (net 2 /MISO)
+  (net 3 /MOSI)
+  (net 4 /SCK)
+  (net 5 /~RST)
+  (net 6 GND)
+  (net 7 N-0000010)
+  (net 8 N-0000011)
+  (net 9 N-0000012)
+  (net 10 N-0000013)
+  (net 11 N-0000014)
+  (net 12 N-0000015)
+  (net 13 N-0000016)
+  (net 14 N-000008)
+  (net 15 N-000009)
+
+  (net_class Default "This is the default net class."
+    (clearance 0.254)
+    (trace_width 0.635)
+    (via_dia 0.889)
+    (via_drill 0.635)
+    (uvia_dia 0.508)
+    (uvia_drill 0.127)
+    (add_net "")
+    (add_net +5V)
+    (add_net /MISO)
+    (add_net /MOSI)
+    (add_net /SCK)
+    (add_net /~RST)
+    (add_net GND)
+    (add_net N-0000010)
+    (add_net N-0000011)
+    (add_net N-0000012)
+    (add_net N-0000013)
+    (add_net N-0000014)
+    (add_net N-0000015)
+    (add_net N-0000016)
+    (add_net N-000008)
+    (add_net N-000009)
+  )
+
+  (module DCJACK_2PIN (layer F.Cu) (tedit 5240C1EC) (tstamp 5240C0DC)
+    (at 56.05 76.2 270)
+    (path /5240B8CC)
+    (fp_text reference P1 (at -2.05 3.7 360) (layer F.SilkS)
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text value CONN_2 (at 7.8994 6.79958 270) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_line (start 0 -2.70002) (end 0 -4.50088) (layer F.SilkS) (width 0.381))
+    (fp_line (start 0 -4.50088) (end 13.79982 -4.50088) (layer F.SilkS) (width 0.381))
+    (fp_line (start 13.79982 -4.50088) (end 13.79982 4.39928) (layer F.SilkS) (width 0.381))
+    (fp_line (start 13.79982 4.39928) (end 13.79982 4.50088) (layer F.SilkS) (width 0.381))
+    (fp_line (start 13.79982 4.50088) (end 0 4.50088) (layer F.SilkS) (width 0.381))
+    (fp_line (start 0 4.50088) (end 0 2.70002) (layer F.SilkS) (width 0.381))
+    (pad 1 thru_hole circle (at 0 0 270) (size 5.08 5.08) (drill 2.99974)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 6 GND)
+    )
+    (pad 2 thru_hole circle (at 5.99948 0 270) (size 4.59994 4.59994) (drill 2.60096)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 +5V)
+    )
+  )
+
+  (module 3X2_SHRD_HEADER (layer F.Cu) (tedit 5240C1F1) (tstamp 5240C0F0)
+    (at 77.3 73.4 180)
+    (path /5240BA0F)
+    (fp_text reference P2 (at 9.6 4.1 180) (layer F.SilkS)
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text value CONN_3X2 (at 5.19938 6.2992 180) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text user 5 (at 2.54 3.556 180) (layer F.SilkS)
+      (effects (font (size 1.27 1.27) (thickness 0.254)))
+    )
+    (fp_text user 6 (at 2.54 -3.302 180) (layer F.SilkS)
+      (effects (font (size 1.27 1.27) (thickness 0.254)))
+    )
+    (fp_line (start -7.62 4.826) (end 7.62 4.826) (layer F.SilkS) (width 0.381))
+    (fp_line (start -7.62 -4.826) (end 7.62 -4.826) (layer F.SilkS) (width 0.381))
+    (fp_line (start 7.62 -4.826) (end 7.62 4.826) (layer F.SilkS) (width 0.381))
+    (fp_line (start -7.62 4.826) (end -7.62 -4.826) (layer F.SilkS) (width 0.381))
+    (fp_line (start -4.36118 7.29996) (end -1.3589 7.29996) (layer F.SilkS) (width 0.381))
+    (fp_text user 2 (at -2.54 -3.302 180) (layer F.SilkS)
+      (effects (font (size 1.27 1.27) (thickness 0.254)))
+    )
+    (fp_line (start -2.82448 5.48894) (end -4.34848 7.26694) (layer F.SilkS) (width 0.381))
+    (fp_line (start -1.30048 7.2644) (end -2.82448 5.4864) (layer F.SilkS) (width 0.381))
+    (pad 1 thru_hole rect (at -2.54 1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 2 /MISO)
+    )
+    (pad 2 thru_hole circle (at -2.54 -1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 +5V)
+    )
+    (pad 3 thru_hole circle (at 0 1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 4 /SCK)
+    )
+    (pad 4 thru_hole circle (at 0 -1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 3 /MOSI)
+    )
+    (pad 5 thru_hole circle (at 2.54 1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 5 /~RST)
+    )
+    (pad 6 thru_hole circle (at 2.54 -1.27 180) (size 1.778 1.778) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 6 GND)
+    )
+  )
+
+  (module HEADER_TOP (layer F.Cu) (tedit 5240C200) (tstamp 5240C10D)
+    (at 70 58.2)
+    (path /5240B882)
+    (fp_text reference P3 (at -17.8 2.85) (layer F.SilkS)
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_text value CONN15 (at 7.62 -4.572) (layer F.SilkS) hide
+      (effects (font (thickness 0.3048)))
+    )
+    (fp_line (start 15.24 -8.128) (end 19.05 -8.128) (layer F.SilkS) (width 0.381))
+    (fp_line (start 19.05 -8.128) (end 19.05 -7.366) (layer F.SilkS) (width 0.381))
+    (fp_line (start -15.24 -8.128) (end -19.05 -8.128) (layer F.SilkS) (width 0.381))
+    (fp_line (start -19.05 -8.128) (end -19.05 -7.62) (layer F.SilkS) (width 0.381))
+    (fp_line (start -15.24 1.27) (end -19.05 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start -19.05 1.27) (end -19.05 -7.62) (layer F.SilkS) (width 0.381))
+    (fp_line (start 15.24 1.27) (end 19.05 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start 19.05 1.27) (end 19.05 -7.62) (layer F.SilkS) (width 0.381))
+    (fp_line (start 15.24 1.27) (end -15.24 1.27) (layer F.SilkS) (width 0.381))
+    (fp_line (start -15.24 -8.128) (end 15.24 -8.128) (layer F.SilkS) (width 0.381))
+    (pad 1 thru_hole rect (at -17.78 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 1 +5V)
+    )
+    (pad 2 thru_hole circle (at -15.24 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 6 GND)
+    )
+    (pad 3 thru_hole circle (at -12.7 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 5 /~RST)
+    )
+    (pad 4 thru_hole circle (at -10.16 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 4 /SCK)
+    )
+    (pad 5 thru_hole circle (at -7.62 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 3 /MOSI)
+    )
+    (pad 6 thru_hole circle (at -5.08 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 2 /MISO)
+    )
+    (pad 7 thru_hole circle (at -2.54 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 13 N-0000016)
+    )
+    (pad 8 thru_hole circle (at 0 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 12 N-0000015)
+    )
+    (pad 9 thru_hole circle (at 2.54 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 11 N-0000014)
+    )
+    (pad 10 thru_hole circle (at 5.08 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 10 N-0000013)
+    )
+    (pad 11 thru_hole circle (at 7.62 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 9 N-0000012)
+    )
+    (pad 12 thru_hole circle (at 10.16 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 8 N-0000011)
+    )
+    (pad 13 thru_hole circle (at 12.7 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 7 N-0000010)
+    )
+    (pad 14 thru_hole circle (at 15.24 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 15 N-000009)
+    )
+    (pad 15 thru_hole circle (at 17.78 0) (size 1.524 1.524) (drill 1.016)
+      (layers *.Cu *.Mask F.SilkS)
+      (net 14 N-000008)
+    )
+  )
+
+  (gr_text www.iorodeo.com (at 79.75 87.85) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.254)))
+  )
+  (gr_text AVRISP (at 77.95 79.9) (layer F.SilkS)
+    (effects (font (size 1.27 1.27) (thickness 0.254)))
+  )
+  (gr_line (start 90 90) (end 90 50) (angle 90) (layer Edge.Cuts) (width 0.3))
+  (gr_line (start 50 90) (end 90 90) (angle 90) (layer Edge.Cuts) (width 0.3))
+  (gr_line (start 50 50) (end 50 90) (angle 90) (layer Edge.Cuts) (width 0.3))
+  (gr_line (start 90 50) (end 50 50) (angle 90) (layer Edge.Cuts) (width 0.3))
+
+)

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.net

+(export (version D)
+  (design
+    (source /home/wbd/work/iorodeo/products/panels_g4_hardware/atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.sch)
+    (date "Mon 23 Sep 2013 03:08:41 PM PDT")
+    (tool "eeschema (2013-mar-13)-testing"))
+  (components
+    (comp (ref P3)
+      (value CONN15)
+      (libsource (lib conn15) (part CONN15))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5240B882))
+    (comp (ref P1)
+      (value CONN_2)
+      (libsource (lib conn) (part CONN_2))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5240B8CC))
+    (comp (ref P2)
+      (value CONN_3X2)
+      (libsource (lib conn) (part CONN_3X2))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5240BA0F)))
+  (libparts
+    (libpart (lib conn) (part CONN_2)
+      (description "Symbole general de connecteur")
+      (fields
+        (field (name Reference) P)
+        (field (name Value) CONN_2))
+      (pins
+        (pin (num 1) (name P1) (type passive))
+        (pin (num 2) (name PM) (type passive))))
+    (libpart (lib conn) (part CONN_3X2)
+      (description "Symbole general de connecteur")
+      (fields
+        (field (name Reference) P)
+        (field (name Value) CONN_3X2))
+      (pins
+        (pin (num 1) (name 1) (type passive))
+        (pin (num 2) (name 2) (type passive))
+        (pin (num 3) (name 3) (type passive))
+        (pin (num 4) (name 4) (type passive))
+        (pin (num 5) (name 5) (type passive))
+        (pin (num 6) (name 6) (type passive))))
+    (libpart (lib conn15) (part CONN15)
+      (fields
+        (field (name Reference) P)
+        (field (name Value) CONN15))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))
+        (pin (num 3) (name ~) (type passive))
+        (pin (num 4) (name ~) (type passive))
+        (pin (num 5) (name ~) (type passive))
+        (pin (num 6) (name ~) (type passive))
+        (pin (num 7) (name ~) (type passive))
+        (pin (num 8) (name ~) (type passive))
+        (pin (num 9) (name ~) (type passive))
+        (pin (num 10) (name ~) (type passive))
+        (pin (num 11) (name ~) (type passive))
+        (pin (num 12) (name ~) (type input))
+        (pin (num 13) (name ~) (type passive))
+        (pin (num 14) (name ~) (type passive))
+        (pin (num 15) (name ~) (type passive)))))
+  (libraries
+    (library (logical conn)
+      (uri /usr/share/kicad/library/conn.lib))
+    (library (logical conn15)
+      (uri conn15.lib)))
+  (nets
+    (net (code 1) (name GND)
+      (node (ref P3) (pin 2))
+      (node (ref P1) (pin 1))
+      (node (ref P2) (pin 6)))
+    (net (code 2) (name +5V)
+      (node (ref P1) (pin 2))
+      (node (ref P2) (pin 2))
+      (node (ref P3) (pin 1)))
+    (net (code 3) (name /MOSI)
+      (node (ref P3) (pin 5))
+      (node (ref P2) (pin 4)))
+    (net (code 4) (name /~RST)
+      (node (ref P3) (pin 3))
+      (node (ref P2) (pin 5)))
+    (net (code 5) (name /SCK)
+      (node (ref P2) (pin 3))
+      (node (ref P3) (pin 4)))
+    (net (code 6) (name /MISO)
+      (node (ref P2) (pin 1))
+      (node (ref P3) (pin 6)))
+    (net (code 8) (name "")
+      (node (ref P3) (pin 15)))
+    (net (code 9) (name "")
+      (node (ref P3) (pin 14)))
+    (net (code 10) (name "")
+      (node (ref P3) (pin 13)))
+    (net (code 11) (name "")
+      (node (ref P3) (pin 12)))
+    (net (code 12) (name "")
+      (node (ref P3) (pin 11)))
+    (net (code 13) (name "")
+      (node (ref P3) (pin 10)))
+    (net (code 14) (name "")
+      (node (ref P3) (pin 9)))
+    (net (code 15) (name "")
+      (node (ref P3) (pin 8)))
+    (net (code 16) (name "")
+      (node (ref P3) (pin 7)))))

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.pro

+update=Mon 23 Sep 2013 03:20:11 PM PDT
+version=1
+last_client=pcbnew
+[cvpcb]
+version=1
+NetIExt=net
+[cvpcb/libraries]
+EquName1=devcms
+[general]
+version=1
+[eeschema]
+version=1
+LibDir=
+NetFmtName=
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=conn15
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill="    0.600000"
+PadDrillOvalY="    0.600000"
+PadSizeH="    1.500000"
+PadSizeV="    1.500000"
+PcbTextSizeV="    1.500000"
+PcbTextSizeH="    1.500000"
+PcbTextThickness="    0.300000"
+ModuleTextSizeV="    1.000000"
+ModuleTextSizeH="    1.000000"
+ModuleTextSizeThickness="    0.150000"
+SolderMaskClearance="    0.000000"
+SolderMaskMinWidth="    0.000000"
+DrawSegmentWidth="    0.200000"
+BoardOutlineThickness="    0.100000"
+ModuleOutlineThickness="    0.381000"
+[pcbnew/libraries]
+LibDir=
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=smd_capacitors
+LibName7=smd_resistors
+LibName8=smd_crystal&oscillator
+LibName9=smd_dil
+LibName10=smd_transistors
+LibName11=libcms
+LibName12=display
+LibName13=led
+LibName14=dip_sockets
+LibName15=pga_sockets
+LibName16=valves
+LibName17=DCJACK_2PIN
+LibName18=HEADER_TOP
+LibName19=3X2_SHRD_HEADER

atmega328/four_panel/20mm_matrix/programmer/comm_programmer/programmer.sch

+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface