Commits

iorodeo committed f7b6085 Draft

Finished test arena for 4 x 20mm atmega328 panels.

Comments (0)

Files changed (17)

atmega328/four_panel/20mm_matrix/test_arena/CAPACITOR_POLARIZED.mod

+PCBNEW-LibModule-V1  Wed 02 Oct 2013 11:36:53 AM PDT
+# encoding utf-8
+Units mm
+$INDEX
+Capacitor_Polarized
+$EndINDEX
+$MODULE Capacitor_Polarized
+Po 0 0 0 15 4D1A80BA 00000000 ~~
+Li Capacitor_Polarized
+Cd ELECTROLYTIC CAPACITOR
+Kw ELECTROLYTIC CAPACITOR
+Sc 0
+AR 
+Op 0 0 0
+At VIRTUAL
+T0 -11.684 -0.508 1.524 1.524 0 0.3048 N V 21 N "CapacitorPolarized"
+T1 0 7.62 1.524 1.524 0 0.3048 N I 21 N "VAL**"
+DC 0 0 1.27 -5.08 0.381 21
+DS 0.254 1.143 0.889 1.143 0.2032 21
+DS 0.889 1.143 0.889 -1.143 0.2032 21
+DS 0.254 -1.143 0.889 -1.143 0.2032 21
+DS 0.254 1.143 0.254 -1.143 0.2032 21
+DS -1.143 0 -0.889 0 0.1524 21
+DS -0.889 0 -0.889 1.143 0.1524 21
+DS -0.889 1.143 -0.254 1.143 0.1524 21
+DS -0.254 1.143 -0.254 -1.143 0.1524 21
+DS -0.254 -1.143 -0.889 -1.143 0.1524 21
+DS -0.889 -1.143 -0.889 0 0.1524 21
+DS 0.635 0 1.143 0 0.1524 21
+DS -6.35 -0.381 -6.35 0.381 0.1524 21
+DS -5.969 0 -6.731 0 0.1524 21
+DS 1.143 0 1.651 0 0.1524 21
+DS -1.651 0 -1.143 0 0.1524 21
+$PAD
+Sh "1" C 2.54 2.54 0 0 0
+Dr 1.016 0 0
+At STD N 00F0FFFF
+Ne 0 ""
+Po -2.54 0
+$EndPAD
+$PAD
+Sh "2" C 2.54 2.54 0 0 0
+Dr 1.016 0 0
+At STD N 00F0FFFF
+Ne 0 ""
+Po 2.54 0
+$EndPAD
+$EndMODULE Capacitor_Polarized
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/test_arena/DCJACK_2PIN.mod

+PCBNEW-LibModule-V1  Thu 21 Jun 2012 04:30:35 PM PDT
+# encoding utf-8
+$INDEX
+DCJACK_2PIN
+$EndINDEX
+$MODULE DCJACK_2PIN
+Po 0 0 0 15 4CFD9C4C 4FE3AE85 ~~
+Li DCJACK_2PIN
+Sc 4FE3AE85
+AR 
+Op 0 0 0
+T0 2913 -2913 600 600 0 120 N V 21 N "DCJACK_2PIN"
+T1 3110 2677 600 600 0 120 N I 21 N "VAL**"
+DS 0 -1063 0 -1772 150 21
+DS 0 -1772 5433 -1772 150 21
+DS 5433 -1772 5433 1732 150 21
+DS 5433 1732 5433 1772 150 21
+DS 5433 1772 0 1772 150 21
+DS 0 1772 0 1063 150 21
+$PAD
+Sh "1" C 2000 2000 0 0 0
+Dr 1181 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 0 0
+$EndPAD
+$PAD
+Sh "2" C 1811 1811 0 0 0
+Dr 1024 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 2362 0
+$EndPAD
+$EndMODULE  DCJACK_2PIN
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/test_arena/HEADER_TOP.mod

+PCBNEW-LibModule-V1  Wed 02 Oct 2013 12:54:59 PM PDT
+# encoding utf-8
+Units mm
+$INDEX
+HEADER_TOP
+$EndINDEX
+$MODULE HEADER_TOP
+Po 0 0 0 15 524C7A10 00000000 ~~
+Li HEADER_TOP
+Sc 0
+AR HEADER_TOP
+Op 0 0 0
+T0 -6.604 -4.826 1.524 1.524 0 0.3048 N V 21 N "HEADER_TOP"
+T1 7.62 -4.572 1.524 1.524 0 0.3048 N V 21 N "VAL**"
+DS -19.9898 0.8382 -19.9898 0.6858 0.381 21
+DS -19.9898 0.9398 -19.9898 0.7366 0.381 21
+DS 19.0246 -8.128 19.9898 -8.128 0.381 21
+DS 19.9898 1.27 19.9898 0.6858 0.381 21
+DS 19.9898 -8.1026 19.9898 -7.5946 0.381 21
+DS -19.9898 -8.128 -19.9898 -7.5946 0.381 21
+DS -19.9898 1.27 -19.9898 0.8382 0.381 21
+DS -18.796 -8.128 -19.9771 -8.128 0.381 21
+DS -18.9611 1.27 -19.9898 1.27 0.381 21
+DS 18.9865 1.27 19.9898 1.27 0.381 21
+DS 15.24 -8.128 19.05 -8.128 0.381 21
+DS 19.05 -8.128 19.05 -7.366 0.381 21
+DS -15.24 -8.128 -19.05 -8.128 0.381 21
+DS -19.05 -8.128 -19.05 -7.62 0.381 21
+DS -15.24 1.27 -19.05 1.27 0.381 21
+DS -19.05 1.27 -19.05 -7.62 0.381 21
+DS 15.24 1.27 19.05 1.27 0.381 21
+DS 19.05 1.27 19.05 -7.62 0.381 21
+DS 15.24 1.27 -15.24 1.27 0.381 21
+DS -15.24 -8.128 15.24 -8.128 0.381 21
+$PAD
+Sh "1" R 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -17.78 0
+$EndPAD
+$PAD
+Sh "2" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -15.24 0
+$EndPAD
+$PAD
+Sh "3" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -12.7 0
+$EndPAD
+$PAD
+Sh "4" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -10.16 0
+$EndPAD
+$PAD
+Sh "5" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -7.62 0
+$EndPAD
+$PAD
+Sh "6" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -5.08 0
+$EndPAD
+$PAD
+Sh "7" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -2.54 0
+$EndPAD
+$PAD
+Sh "8" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 0 0
+$EndPAD
+$PAD
+Sh "9" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 2.54 0
+$EndPAD
+$PAD
+Sh "10" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 5.08 0
+$EndPAD
+$PAD
+Sh "11" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 7.62 0
+$EndPAD
+$PAD
+Sh "12" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 10.16 0
+$EndPAD
+$PAD
+Sh "13" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 12.7 0
+$EndPAD
+$PAD
+Sh "14" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 15.24 0
+$EndPAD
+$PAD
+Sh "15" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 17.78 0
+$EndPAD
+$EndMODULE HEADER_TOP
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/test_arena/MOUNT_HOLE_4_40.mod

+PCBNEW-LibModule-V1  Thu 20 Oct 2011 03:55:17 PM PDT
+# encoding utf-8
+$INDEX
+MOUNT_HOLE_4_40
+$EndINDEX
+$MODULE MOUNT_HOLE_4_40
+Po 0 0 0 15 4C193599 4EA0A6A0 ~~
+Li MOUNT_HOLE_4_40
+Sc 4EA0A6A0
+AR MOUNT_HOLE_4_40
+Op 0 0 0
+T0 0 -800 100 100 0 25 N I 21 N "MOUNT_HOLE"
+T1 0 800 100 100 0 25 N I 21 N "VAL**"
+$PAD
+Sh "" C 1300 1300 0 0 0
+Dr 1200 0 0
+At STD N 00F0FFFF
+Ne 0 ""
+Po 0 0
+$EndPAD
+$EndMODULE  MOUNT_HOLE_4_40
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/test_arena/PIN_ARRAY_SHRD_20X2.mod

+PCBNEW-LibModule-V1  Wed 02 Oct 2013 12:08:01 PM PDT
+# encoding utf-8
+Units mm
+$INDEX
+PIN_ARRAY_SHRD_20X2
+$EndINDEX
+$MODULE PIN_ARRAY_SHRD_20X2
+Po 0 0 0 15 524C6F05 00000000 ~~
+Li PIN_ARRAY_SHRD_20X2
+Cd Pin array 20x2 with shroud
+Kw CONN
+Sc 0
+AR 
+Op 0 0 0
+T0 0 -5.49 1.016 1.016 0 0.27432 N V 21 N "REF*"
+T1 0.04 6.21 1.016 1.016 0 0.2032 N V 21 N "PIN_ARRAY_SHRD_20X2"
+DS -23.368 5.588 -23.622 5.588 0.3 21
+DS -24.13 5.08 -23.368 5.588 0.3 21
+DS -24.13 5.08 -24.892 5.588 0.3 21
+DS -24.892 5.588 -23.495 5.588 0.3 21
+DS 0.01 4.5 29.21 4.5 0.3 21
+DS 29.21 4.5 29.21 -4.5 0.3 21
+DS 29.21 -4.5 -0.01 -4.5 0.3 21
+DS -29.21 0 -29.21 4.5 0.3 21
+DS -29.21 4.5 0.01 4.5 0.3 21
+DS -29.21 0 -29.21 -4.5 0.3 21
+DS -29.21 -4.5 -0.01 -4.5 0.3 21
+$PAD
+Sh "1" R 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -24.13 1.27
+$EndPAD
+$PAD
+Sh "2" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po -24.13 -1.27
+$EndPAD
+$PAD
+Sh "11" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 18 "PA8_1"
+Po -11.43 1.27
+$EndPAD
+$PAD
+Sh "4" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 11 "PA1_1"
+Po -21.59 -1.27
+$EndPAD
+$PAD
+Sh "13" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 5 "PA10_1"
+Po -8.89 1.27
+$EndPAD
+$PAD
+Sh "6" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 13 "PA3_1"
+Po -19.05 -1.27
+$EndPAD
+$PAD
+Sh "15" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 7 "PA12_1"
+Po -6.35 1.27
+$EndPAD
+$PAD
+Sh "8" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 15 "PA5_1"
+Po -16.51 -1.27
+$EndPAD
+$PAD
+Sh "17" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 9 "PA14_1"
+Po -3.81 1.27
+$EndPAD
+$PAD
+Sh "10" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 17 "PA7_1"
+Po -13.97 -1.27
+$EndPAD
+$PAD
+Sh "19" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -1.27 1.27
+$EndPAD
+$PAD
+Sh "12" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 19 "PA9_1"
+Po -11.43 -1.27
+$EndPAD
+$PAD
+Sh "21" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 1.27 1.27
+$EndPAD
+$PAD
+Sh "14" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 6 "PA11_1"
+Po -8.89 -1.27
+$EndPAD
+$PAD
+Sh "23" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 2 "INT1_1"
+Po 3.81 1.27
+$EndPAD
+$PAD
+Sh "16" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 8 "PA13_1"
+Po -6.35 -1.27
+$EndPAD
+$PAD
+Sh "25" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 6.35 1.27
+$EndPAD
+$PAD
+Sh "18" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 10 "PA15_1"
+Po -3.81 -1.27
+$EndPAD
+$PAD
+Sh "27" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 8.89 1.27
+$EndPAD
+$PAD
+Sh "20" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -1.27 -1.27
+$EndPAD
+$PAD
+Sh "29" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 22 "VCC"
+Po 11.43 1.27
+$EndPAD
+$PAD
+Sh "22" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 1.27 -1.27
+$EndPAD
+$PAD
+Sh "31" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 22 "VCC"
+Po 13.97 1.27
+$EndPAD
+$PAD
+Sh "24" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 3 "INT2_1"
+Po 3.81 -1.27
+$EndPAD
+$PAD
+Sh "26" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 6.35 -1.27
+$EndPAD
+$PAD
+Sh "33" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 21 "Tin1_cold_1"
+Po 16.51 1.27
+$EndPAD
+$PAD
+Sh "28" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 10 "PA15_1"
+Po 8.89 -1.27
+$EndPAD
+$PAD
+Sh "32" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po 13.97 -1.27
+$EndPAD
+$PAD
+Sh "34" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 16.51 -1.27
+$EndPAD
+$PAD
+Sh "36" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 19.05 -1.27
+$EndPAD
+$PAD
+Sh "38" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 21.59 -1.27
+$EndPAD
+$PAD
+Sh "35" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 19.05 1.27
+$EndPAD
+$PAD
+Sh "37" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 20 "PB4_1"
+Po 21.59 1.27
+$EndPAD
+$PAD
+Sh "3" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 4 "PA0_1"
+Po -21.59 1.27
+$EndPAD
+$PAD
+Sh "5" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 12 "PA2_1"
+Po -19.05 1.27
+$EndPAD
+$PAD
+Sh "7" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 14 "PA4_1"
+Po -16.51 1.27
+$EndPAD
+$PAD
+Sh "9" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 16 "PA6_1"
+Po -13.97 1.27
+$EndPAD
+$PAD
+Sh "39" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 24.13 1.27
+$EndPAD
+$PAD
+Sh "40" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 24.13 -1.27
+$EndPAD
+$PAD
+Sh "30" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po 11.43 -1.27
+$EndPAD
+$SHAPE3D
+Na "pin_array/pins_array_20x2.wrl"
+Sc 1 1 1
+Of 0 0 0
+Ro 0 0 0
+$EndSHAPE3D
+$EndMODULE PIN_ARRAY_SHRD_20X2
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/test_arena/PIN_ARRAY_SHRD_30X2.mod

+PCBNEW-LibModule-V1  Wed 02 Oct 2013 11:57:51 AM PDT
+# encoding utf-8
+Units mm
+$INDEX
+PIN_ARRAY_SHRD_30X2
+$EndINDEX
+$MODULE PIN_ARRAY_SHRD_30X2
+Po 0 0 0 15 524C6C95 00000000 ~~
+Li PIN_ARRAY_SHRD_30X2
+Cd pin array 30X2 with shroud
+Kw CONN
+Sc 0
+AR 
+Op 0 0 0
+T0 0.05 -5.5 1.016 1.016 0 0.27432 N V 21 N "REF*"
+T1 0.05 5.8 1.016 1.016 0 0.2032 N V 21 N "PIN_ARRAY_SHRD_30X2"
+DS -36.83 5.08 -36.068 5.588 0.3 21
+DS -36.195 5.588 -37.592 5.588 0.3 21
+DS -36.83 5.08 -37.592 5.588 0.3 21
+DS 41.9 -4.5 -0.05 -4.5 0.3 21
+DS 41.9 4.5 41.9 -4.5 0.3 21
+DS 0 4.5 41.9 4.5 0.3 21
+DS -41.9 4.5 0 4.5 0.3 21
+DS -41.9 0 -41.9 4.5 0.3 21
+DS -41.9 -4.5 -0.05 -4.5 0.3 21
+DS -41.9 0 -41.9 -4.5 0.3 21
+$PAD
+Sh "1" R 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -36.83 1.27
+$EndPAD
+$PAD
+Sh "2" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po -36.83 -1.27
+$EndPAD
+$PAD
+Sh "11" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 18 "PA8_1"
+Po -24.13 1.27
+$EndPAD
+$PAD
+Sh "4" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 11 "PA1_1"
+Po -34.29 -1.27
+$EndPAD
+$PAD
+Sh "13" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 5 "PA10_1"
+Po -21.59 1.27
+$EndPAD
+$PAD
+Sh "6" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 13 "PA3_1"
+Po -31.75 -1.27
+$EndPAD
+$PAD
+Sh "15" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 7 "PA12_1"
+Po -19.05 1.27
+$EndPAD
+$PAD
+Sh "8" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 15 "PA5_1"
+Po -29.21 -1.27
+$EndPAD
+$PAD
+Sh "17" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 9 "PA14_1"
+Po -16.51 1.27
+$EndPAD
+$PAD
+Sh "10" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 17 "PA7_1"
+Po -26.67 -1.27
+$EndPAD
+$PAD
+Sh "19" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -13.97 1.27
+$EndPAD
+$PAD
+Sh "12" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 19 "PA9_1"
+Po -24.13 -1.27
+$EndPAD
+$PAD
+Sh "21" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -11.43 1.27
+$EndPAD
+$PAD
+Sh "14" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 6 "PA11_1"
+Po -21.59 -1.27
+$EndPAD
+$PAD
+Sh "23" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 2 "INT1_1"
+Po -8.89 1.27
+$EndPAD
+$PAD
+Sh "16" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 8 "PA13_1"
+Po -19.05 -1.27
+$EndPAD
+$PAD
+Sh "25" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -6.35 1.27
+$EndPAD
+$PAD
+Sh "18" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 10 "PA15_1"
+Po -16.51 -1.27
+$EndPAD
+$PAD
+Sh "27" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -3.81 1.27
+$EndPAD
+$PAD
+Sh "20" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -13.97 -1.27
+$EndPAD
+$PAD
+Sh "29" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 22 "VCC"
+Po -1.27 1.27
+$EndPAD
+$PAD
+Sh "22" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -11.43 -1.27
+$EndPAD
+$PAD
+Sh "31" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 22 "VCC"
+Po 1.27 1.27
+$EndPAD
+$PAD
+Sh "24" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 3 "INT2_1"
+Po -8.89 -1.27
+$EndPAD
+$PAD
+Sh "26" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po -6.35 -1.27
+$EndPAD
+$PAD
+Sh "33" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 21 "Tin1_cold_1"
+Po 3.81 1.27
+$EndPAD
+$PAD
+Sh "28" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 10 "PA15_1"
+Po -3.81 -1.27
+$EndPAD
+$PAD
+Sh "32" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po 1.27 -1.27
+$EndPAD
+$PAD
+Sh "34" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 3.81 -1.27
+$EndPAD
+$PAD
+Sh "36" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 6.35 -1.27
+$EndPAD
+$PAD
+Sh "38" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 8.89 -1.27
+$EndPAD
+$PAD
+Sh "35" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 6.35 1.27
+$EndPAD
+$PAD
+Sh "37" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 20 "PB4_1"
+Po 8.89 1.27
+$EndPAD
+$PAD
+Sh "3" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 4 "PA0_1"
+Po -34.29 1.27
+$EndPAD
+$PAD
+Sh "5" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 12 "PA2_1"
+Po -31.75 1.27
+$EndPAD
+$PAD
+Sh "7" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 14 "PA4_1"
+Po -29.21 1.27
+$EndPAD
+$PAD
+Sh "9" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 16 "PA6_1"
+Po -26.67 1.27
+$EndPAD
+$PAD
+Sh "39" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 11.43 1.27
+$EndPAD
+$PAD
+Sh "40" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 11.43 -1.27
+$EndPAD
+$PAD
+Sh "30" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 1 "GND"
+Po -1.27 -1.27
+$EndPAD
+$PAD
+Sh "41" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 13.97 1.27
+$EndPAD
+$PAD
+Sh "42" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 13.97 -1.27
+$EndPAD
+$PAD
+Sh "43" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 16.51 1.27
+$EndPAD
+$PAD
+Sh "44" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 16.51 -1.27
+$EndPAD
+$PAD
+Sh "45" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 19.05 1.27
+$EndPAD
+$PAD
+Sh "46" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 19.05 -1.27
+$EndPAD
+$PAD
+Sh "47" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 21.59 1.27
+$EndPAD
+$PAD
+Sh "48" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 21.59 -1.27
+$EndPAD
+$PAD
+Sh "49" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 24.13 1.27
+$EndPAD
+$PAD
+Sh "50" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 24.13 -1.27
+$EndPAD
+$PAD
+Sh "51" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 26.67 1.27
+$EndPAD
+$PAD
+Sh "52" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 26.67 -1.27
+$EndPAD
+$PAD
+Sh "53" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 29.21 1.27
+$EndPAD
+$PAD
+Sh "54" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 29.21 -1.27
+$EndPAD
+$PAD
+Sh "55" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 31.75 1.27
+$EndPAD
+$PAD
+Sh "56" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 31.75 -1.27
+$EndPAD
+$PAD
+Sh "57" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 34.29 1.27
+$EndPAD
+$PAD
+Sh "58" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 34.29 -1.27
+$EndPAD
+$PAD
+Sh "59" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 36.83 1.27
+$EndPAD
+$PAD
+Sh "60" C 1.524 1.524 0 0 0
+Dr 1.016 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 36.83 -1.27
+$EndPAD
+$SHAPE3D
+Na "pin_array/pins_array_30x2.wrl"
+Sc 1 1 1
+Of 0 0 0
+Ro 0 0 0
+$EndSHAPE3D
+$EndMODULE PIN_ARRAY_SHRD_30X2
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/test_arena/QTR_TWENTY.mod

+PCBNEW-LibModule-V1  Wed 02 Oct 2013 01:59:29 PM PDT
+# encoding utf-8
+Units mm
+$INDEX
+1/4-20
+$EndINDEX
+$MODULE 1/4-20
+Po 0 0 0 15 4E2F71AA 00000000 ~~
+Li 1/4-20
+Sc 0
+AR 
+Op 0 0 0
+T0 0 -6.35 1.524 1.524 0 0.3048 N V 21 N "1/4-20"
+T1 1.27 6.35 1.524 1.524 0 0.3048 N V 21 N "VAL**"
+DC 0 0 5.461 0.635 0.381 21
+$PAD
+Sh "" C 8.128 8.128 0 0 0
+Dr 6.604 0 0
+At STD N 00E0FFFF
+Ne 0 ""
+Po 0 0
+$EndPAD
+$EndMODULE 1/4-20
+$EndLIBRARY

atmega328/four_panel/20mm_matrix/test_arena/arena-cache.lib

-EESchema-LIBRARY Version 2.3  Date: Tue 01 Oct 2013 11:27:32 PM PDT
+EESchema-LIBRARY Version 2.3  Date: Wed 02 Oct 2013 12:10:44 PM PDT
 #encoding utf-8
 #
 # +5V

atmega328/four_panel/20mm_matrix/test_arena/arena.bak

 LIBS:contrib
 LIBS:valves
 LIBS:conn15
+LIBS:arena-cache
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 	1    0    0    -1  
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-L GND #PWR7
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 F 2 "" H 2600 1000 60  0000 C CNN
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 Wire Wire Line
 	2600 1300 2600 1450
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-L GND #PWR8
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 U 1 1 524B4A10
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-F 0 "#PWR8" H 2600 1450 30  0001 C CNN
+F 0 "#PWR010" H 2600 1450 30  0001 C CNN
 F 1 "GND" H 2600 1380 30  0001 C CNN
 F 2 "" H 2600 1450 60  0000 C CNN
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 Wire Wire Line
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-F 0 "#PWR3" H 4350 1090 20  0001 C CNN
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 F 2 "" H 4350 1000 60  0000 C CNN
 F 3 "" H 4350 1000 60  0000 C CNN
 Wire Wire Line
 	4350 1300 4350 1450
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-L GND #PWR9
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 F 1 "GND" H 4350 1380 30  0001 C CNN
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 Wire Wire Line
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 F 2 "" H 6100 1000 60  0000 C CNN
 F 3 "" H 6100 1000 60  0000 C CNN
 Wire Wire Line
 	6100 1300 6100 1450
 $Comp
-L GND #PWR10
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 P 6100 1450
-F 0 "#PWR10" H 6100 1450 30  0001 C CNN
+F 0 "#PWR014" H 6100 1450 30  0001 C CNN
 F 1 "GND" H 6100 1380 30  0001 C CNN
 F 2 "" H 6100 1450 60  0000 C CNN
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 Wire Wire Line
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 F 3 "" H 7800 1000 60  0000 C CNN
 Wire Wire Line
 	7800 1300 7800 1450
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-L GND #PWR11
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 F 1 "GND" H 9450 1380 30  0001 C CNN
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 F 2 "" H 8500 5850 60  0000 C CNN
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 	1    0    0    -1  
 $EndComp
 $Comp
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 	1    0    0    -1  
 $EndComp
 $Comp
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 U 1 1 524B711D
 P 3250 6350
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 F 1 "GND" H 3250 6280 30  0001 C CNN
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 F 3 "" H 3250 6350 60  0000 C CNN
 	1    0    0    -1  
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 F 2 "" H 5000 8950 60  0000 C CNN
 F 3 "" H 5000 8950 60  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR22
+L GND #PWR024
 U 1 1 524BBCDD
 P 5000 10150
-F 0 "#PWR22" H 5000 10150 30  0001 C CNN
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 F 1 "GND" H 5000 10080 30  0001 C CNN
 F 2 "" H 5000 10150 60  0000 C CNN
 F 3 "" H 5000 10150 60  0000 C CNN

atmega328/four_panel/20mm_matrix/test_arena/arena.cmp

+Cmp-Mod V01 Created by CvPcb (2013-mar-13)-testing date = Wed 02 Oct 2013 12:22:02 PM PDT
+
+BeginCmp
+TimeStamp = /524BBC24;
+Reference = C1;
+ValeurCmp = 10uF;
+IdModule  = Capacitor_Polarized;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BBC33;
+Reference = C2;
+ValeurCmp = 10uF;
+IdModule  = Capacitor_Polarized;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BBC42;
+Reference = C3;
+ValeurCmp = 10uF;
+IdModule  = Capacitor_Polarized;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BBC51;
+Reference = C4;
+ValeurCmp = 10uF;
+IdModule  = Capacitor_Polarized;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BBC60;
+Reference = C5;
+ValeurCmp = 10uF;
+IdModule  = Capacitor_Polarized;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B4593;
+Reference = P1;
+ValeurCmp = CONN15;
+IdModule  = HEADER_TOP;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B4A00;
+Reference = P2;
+ValeurCmp = CONN15;
+IdModule  = HEADER_TOP;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B4A5B;
+Reference = P3;
+ValeurCmp = CONN15;
+IdModule  = HEADER_TOP;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B4A8C;
+Reference = P4;
+ValeurCmp = CONN15;
+IdModule  = HEADER_TOP;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B4ABF;
+Reference = P5;
+ValeurCmp = CONN15;
+IdModule  = HEADER_TOP;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B5E2D;
+Reference = P6;
+ValeurCmp = CONN15;
+IdModule  = HEADER_TOP;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BA5BF;
+Reference = P7;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC52;
+Reference = P8;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC64;
+Reference = P9;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC76;
+Reference = P10;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC88;
+Reference = P11;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BA5CE;
+Reference = P12;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC58;
+Reference = P13;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC6A;
+Reference = P14;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC7C;
+Reference = P15;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC8E;
+Reference = P16;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BA5DD;
+Reference = P17;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC5E;
+Reference = P18;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC70;
+Reference = P19;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC82;
+Reference = P20;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524BAC94;
+Reference = P21;
+ValeurCmp = CONN_2X2;
+IdModule  = PIN_ARRAY_2X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B6EC5;
+Reference = P22;
+ValeurCmp = CONN_20X2;
+IdModule  = PIN_ARRAY_SHRD_20X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B6667;
+Reference = P23;
+ValeurCmp = CONN_30X2;
+IdModule  = PIN_ARRAY_SHRD_30X2;
+EndCmp
+
+BeginCmp
+TimeStamp = /524B4691;
+Reference = P24;
+ValeurCmp = CONN_2;
+IdModule  = DCJACK_2PIN;
+EndCmp
+
+EndListe

atmega328/four_panel/20mm_matrix/test_arena/arena.dsn

+(pcb /home/wbd/work/iorodeo/products/panels_g4_hardware/atmega328/four_panel/20mm_matrix/test_arena/arena.dsn
+  (parser
+    (string_quote ")
+    (space_in_quoted_tokens on)
+    (host_cad "KiCad's Pcbnew")
+    (host_version "(2013-mar-13)-testing")
+  )
+  (resolution um 10)
+  (unit um)
+  (structure
+    (layer F.Cu
+      (type signal)
+      (property
+        (index 0)
+      )
+    )
+    (layer B.Cu
+      (type signal)
+      (property
+        (index 1)
+      )
+    )
+    (boundary
+      (path pcb 0  300000 -100000  40000 -100000  40000 -50000  300000 -50000
+            300000 -100000)
+    )
+    (via "Via[0-1]_889:635_um" "Via[0-1]_889:0_um")
+    (rule
+      (width 254)
+      (clearance 254.1)
+      (clearance 254.1 (type default_smd))
+      (clearance 63.5 (type smd_smd))
+    )
+  )
+  (placement
+    (component Capacitor_Polarized
+      (place C1 89000 -76000 front 0 (PN 10uF))
+      (place C2 130000 -76000 front 0 (PN 10uF))
+      (place C3 170000 -76000 front 0 (PN 10uF))
+      (place C4 211000 -76000 front 0 (PN 10uF))
+      (place C5 250000 -76000 front 0 (PN 10uF))
+    )
+    (component PIN_ARRAY_2X2
+      (place P7 102350 -70000 front 0 (PN CONN_2X2))
+      (place P8 142450 -70000 front 0 (PN CONN_2X2))
+      (place P9 182550 -70000 front 0 (PN CONN_2X2))
+      (place P10 222650 -70000 front 0 (PN CONN_2X2))
+      (place P11 262750 -70000 front 0 (PN CONN_2X2))
+      (place P12 109850 -70000 front 0 (PN CONN_2X2))
+      (place P13 149950 -70000 front 0 (PN CONN_2X2))
+      (place P14 190050 -70000 front 0 (PN CONN_2X2))
+      (place P15 230150 -70000 front 0 (PN CONN_2X2))
+      (place P16 270250 -70000 front 0 (PN CONN_2X2))
+      (place P17 117350 -70000 front 0 (PN CONN_2X2))
+      (place P18 157450 -70000 front 0 (PN CONN_2X2))
+      (place P19 197550 -70000 front 0 (PN CONN_2X2))
+      (place P20 237650 -70000 front 0 (PN CONN_2X2))
+      (place P21 277750 -70000 front 0 (PN CONN_2X2))
+    )
+    (component PIN_ARRAY_SHRD_20X2
+      (place P22 117000 -91000 front 0 (PN CONN_20X2))
+    )
+    (component PIN_ARRAY_SHRD_30X2
+      (place P23 237000 -91000 front 0 (PN CONN_30X2))
+    )
+    (component DCJACK_2PIN
+      (place P24 63000 -86000 front 270 (PN CONN_2))
+    )
+    (component HEADER_TOP
+      (place P1 69750 -58100 front 0 (PN CONN15))
+      (place P2 109850 -58100 front 0 (PN CONN15))
+      (place P3 149950 -58100 front 0 (PN CONN15))
+      (place P4 190050 -58100 front 0 (PN CONN15))
+      (place P5 230150 -58100 front 0 (PN CONN15))
+      (place P6 270250 -58100 front 0 (PN CONN15))
+    )
+    (component MOUNT_HOLE_4_40
+      (place M3 297000 -65000 front 0 (PN VAL**))
+      (place M6 43000 -95000 front 0 (PN VAL**))
+      (place M4 297000 -95000 front 0 (PN VAL**))
+      (place M2 170000 -65000 front 0 (PN VAL**))
+      (place M5 170000 -95000 front 0 (PN VAL**))
+      (place M1 43000 -65000 front 0 (PN VAL**))
+    )
+  )
+  (library
+    (image Capacitor_Polarized
+      (outline (path signal 381  5236.34 0  4980.06 -1618.12  4236.29 -3077.85  3077.85 -4236.29
+            1618.12 -4980.06  0 -5236.34  -1618.12 -4980.06  -3077.85 -4236.29
+            -4236.29 -3077.85  -4980.06 -1618.12  -5236.34 0  -4980.06 1618.12
+            -4236.29 3077.85  -3077.85 4236.29  -1618.12 4980.06  0 5236.34
+            1618.12 4980.06  3077.85 4236.29  4236.29 3077.85  4980.06 1618.12))
+      (outline (path signal 203.2  254 -1143  889 -1143))
+      (outline (path signal 203.2  889 -1143  889 1143))
+      (outline (path signal 203.2  254 1143  889 1143))
+      (outline (path signal 203.2  254 -1143  254 1143))
+      (outline (path signal 152.4  -1143 0  -889 0))
+      (outline (path signal 152.4  -889 0  -889 -1143))
+      (outline (path signal 152.4  -889 -1143  -254 -1143))
+      (outline (path signal 152.4  -254 -1143  -254 1143))
+      (outline (path signal 152.4  -254 1143  -889 1143))
+      (outline (path signal 152.4  -889 1143  -889 0))
+      (outline (path signal 152.4  635 0  1143 0))
+      (outline (path signal 152.4  -6350 381  -6350 -381))
+      (outline (path signal 152.4  -5969 0  -6731 0))
+      (outline (path signal 152.4  1143 0  1651 0))
+      (outline (path signal 152.4  -1651 0  -1143 0))
+      (pin Round[A]Pad_2540_um 1 -2540 0)
+      (pin Round[A]Pad_2540_um 2 2540 0)
+    )
+    (image PIN_ARRAY_2X2
+      (outline (path signal 304.8  -2540 2540  2540 2540))
+      (outline (path signal 304.8  2540 2540  2540 -2540))
+      (outline (path signal 304.8  2540 -2540  -2540 -2540))
+      (outline (path signal 304.8  -2540 -2540  -2540 2540))
+      (pin Rect[A]Pad_1524x1524_um 1 -1270 -1270)
+      (pin Round[A]Pad_1524_um 2 -1270 1270)
+      (pin Round[A]Pad_1524_um 3 1270 -1270)
+      (pin Round[A]Pad_1524_um 4 1270 1270)
+    )
+    (image PIN_ARRAY_SHRD_20X2
+      (outline (path signal 300  -23368 -5588  -23622 -5588))
+      (outline (path signal 300  -24130 -5080  -23368 -5588))
+      (outline (path signal 300  -24130 -5080  -24892 -5588))
+      (outline (path signal 300  -24892 -5588  -23495 -5588))
+      (outline (path signal 300  10 -4500  29210 -4500))
+      (outline (path signal 300  29210 -4500  29210 4500))
+      (outline (path signal 300  29210 4500  -10 4500))
+      (outline (path signal 300  -29210 0  -29210 -4500))
+      (outline (path signal 300  -29210 -4500  10 -4500))
+      (outline (path signal 300  -29210 0  -29210 4500))
+      (outline (path signal 300  -29210 4500  -10 4500))
+      (pin Rect[A]Pad_1524x1524_um 1 -24130 -1270)
+      (pin Round[A]Pad_1524_um 2 -24130 1270)
+      (pin Round[A]Pad_1524_um 11 -11430 -1270)
+      (pin Round[A]Pad_1524_um 4 -21590 1270)
+      (pin Round[A]Pad_1524_um 13 -8890 -1270)
+      (pin Round[A]Pad_1524_um 6 -19050 1270)
+      (pin Round[A]Pad_1524_um 15 -6350 -1270)
+      (pin Round[A]Pad_1524_um 8 -16510 1270)
+      (pin Round[A]Pad_1524_um 17 -3810 -1270)
+      (pin Round[A]Pad_1524_um 10 -13970 1270)
+      (pin Round[A]Pad_1524_um 19 -1270 -1270)
+      (pin Round[A]Pad_1524_um 12 -11430 1270)
+      (pin Round[A]Pad_1524_um 21 1270 -1270)
+      (pin Round[A]Pad_1524_um 14 -8890 1270)
+      (pin Round[A]Pad_1524_um 23 3810 -1270)
+      (pin Round[A]Pad_1524_um 16 -6350 1270)
+      (pin Round[A]Pad_1524_um 25 6350 -1270)
+      (pin Round[A]Pad_1524_um 18 -3810 1270)
+      (pin Round[A]Pad_1524_um 27 8890 -1270)
+      (pin Round[A]Pad_1524_um 20 -1270 1270)
+      (pin Round[A]Pad_1524_um 29 11430 -1270)
+      (pin Round[A]Pad_1524_um 22 1270 1270)
+      (pin Round[A]Pad_1524_um 31 13970 -1270)
+      (pin Round[A]Pad_1524_um 24 3810 1270)
+      (pin Round[A]Pad_1524_um 26 6350 1270)
+      (pin Round[A]Pad_1524_um 33 16510 -1270)
+      (pin Round[A]Pad_1524_um 28 8890 1270)
+      (pin Round[A]Pad_1524_um 32 13970 1270)
+      (pin Round[A]Pad_1524_um 34 16510 1270)
+      (pin Round[A]Pad_1524_um 36 19050 1270)
+      (pin Round[A]Pad_1524_um 38 21590 1270)
+      (pin Round[A]Pad_1524_um 35 19050 -1270)
+      (pin Round[A]Pad_1524_um 37 21590 -1270)
+      (pin Round[A]Pad_1524_um 3 -21590 -1270)
+      (pin Round[A]Pad_1524_um 5 -19050 -1270)
+      (pin Round[A]Pad_1524_um 7 -16510 -1270)
+      (pin Round[A]Pad_1524_um 9 -13970 -1270)
+      (pin Round[A]Pad_1524_um 39 24130 -1270)
+      (pin Round[A]Pad_1524_um 40 24130 1270)
+      (pin Round[A]Pad_1524_um 30 11430 1270)
+    )
+    (image PIN_ARRAY_SHRD_30X2
+      (outline (path signal 300  -36830 -5080  -36068 -5588))
+      (outline (path signal 300  -36195 -5588  -37592 -5588))
+      (outline (path signal 300  -36830 -5080  -37592 -5588))
+      (outline (path signal 300  41900 4500  -50 4500))
+      (outline (path signal 300  41900 -4500  41900 4500))
+      (outline (path signal 300  0 -4500  41900 -4500))
+      (outline (path signal 300  -41900 -4500  0 -4500))
+      (outline (path signal 300  -41900 0  -41900 -4500))
+      (outline (path signal 300  -41900 4500  -50 4500))
+      (outline (path signal 300  -41900 0  -41900 4500))
+      (pin Rect[A]Pad_1524x1524_um 1 -36830 -1270)
+      (pin Round[A]Pad_1524_um 2 -36830 1270)
+      (pin Round[A]Pad_1524_um 11 -24130 -1270)
+      (pin Round[A]Pad_1524_um 4 -34290 1270)
+      (pin Round[A]Pad_1524_um 13 -21590 -1270)
+      (pin Round[A]Pad_1524_um 6 -31750 1270)
+      (pin Round[A]Pad_1524_um 15 -19050 -1270)
+      (pin Round[A]Pad_1524_um 8 -29210 1270)
+      (pin Round[A]Pad_1524_um 17 -16510 -1270)
+      (pin Round[A]Pad_1524_um 10 -26670 1270)
+      (pin Round[A]Pad_1524_um 19 -13970 -1270)
+      (pin Round[A]Pad_1524_um 12 -24130 1270)
+      (pin Round[A]Pad_1524_um 21 -11430 -1270)
+      (pin Round[A]Pad_1524_um 14 -21590 1270)
+      (pin Round[A]Pad_1524_um 23 -8890 -1270)
+      (pin Round[A]Pad_1524_um 16 -19050 1270)
+      (pin Round[A]Pad_1524_um 25 -6350 -1270)
+      (pin Round[A]Pad_1524_um 18 -16510 1270)
+      (pin Round[A]Pad_1524_um 27 -3810 -1270)
+      (pin Round[A]Pad_1524_um 20 -13970 1270)
+      (pin Round[A]Pad_1524_um 29 -1270 -1270)
+      (pin Round[A]Pad_1524_um 22 -11430 1270)
+      (pin Round[A]Pad_1524_um 31 1270 -1270)
+      (pin Round[A]Pad_1524_um 24 -8890 1270)
+      (pin Round[A]Pad_1524_um 26 -6350 1270)
+      (pin Round[A]Pad_1524_um 33 3810 -1270)
+      (pin Round[A]Pad_1524_um 28 -3810 1270)
+      (pin Round[A]Pad_1524_um 32 1270 1270)
+      (pin Round[A]Pad_1524_um 34 3810 1270)
+      (pin Round[A]Pad_1524_um 36 6350 1270)
+      (pin Round[A]Pad_1524_um 38 8890 1270)
+      (pin Round[A]Pad_1524_um 35 6350 -1270)
+      (pin Round[A]Pad_1524_um 37 8890 -1270)
+      (pin Round[A]Pad_1524_um 3 -34290 -1270)
+      (pin Round[A]Pad_1524_um 5 -31750 -1270)
+      (pin Round[A]Pad_1524_um 7 -29210 -1270)
+      (pin Round[A]Pad_1524_um 9 -26670 -1270)
+      (pin Round[A]Pad_1524_um 39 11430 -1270)
+      (pin Round[A]Pad_1524_um 40 11430 1270)
+      (pin Round[A]Pad_1524_um 30 -1270 1270)
+      (pin Round[A]Pad_1524_um 41 13970 -1270)
+      (pin Round[A]Pad_1524_um 42 13970 1270)
+      (pin Round[A]Pad_1524_um 43 16510 -1270)
+      (pin Round[A]Pad_1524_um 44 16510 1270)
+      (pin Round[A]Pad_1524_um 45 19050 -1270)
+      (pin Round[A]Pad_1524_um 46 19050 1270)
+      (pin Round[A]Pad_1524_um 47 21590 -1270)
+      (pin Round[A]Pad_1524_um 48 21590 1270)
+      (pin Round[A]Pad_1524_um 49 24130 -1270)
+      (pin Round[A]Pad_1524_um 50 24130 1270)
+      (pin Round[A]Pad_1524_um 51 26670 -1270)
+      (pin Round[A]Pad_1524_um 52 26670 1270)
+      (pin Round[A]Pad_1524_um 53 29210 -1270)
+      (pin Round[A]Pad_1524_um 54 29210 1270)
+      (pin Round[A]Pad_1524_um 55 31750 -1270)
+      (pin Round[A]Pad_1524_um 56 31750 1270)
+      (pin Round[A]Pad_1524_um 57 34290 -1270)
+      (pin Round[A]Pad_1524_um 58 34290 1270)
+      (pin Round[A]Pad_1524_um 59 36830 -1270)
+      (pin Round[A]Pad_1524_um 60 36830 1270)
+    )
+    (image DCJACK_2PIN
+      (outline (path signal 381  0 2700.02  0 4500.88))
+      (outline (path signal 381  0 4500.88  13799.8 4500.88))
+      (outline (path signal 381  13799.8 4500.88  13799.8 -4399.28))
+      (outline (path signal 381  13799.8 -4399.28  13799.8 -4500.88))
+      (outline (path signal 381  13799.8 -4500.88  0 -4500.88))
+      (outline (path signal 381  0 -4500.88  0 -2700.02))
+      (pin Round[A]Pad_5080_um 1 0 0)
+      (pin Round[A]Pad_4599.94_um 2 5999.48 0)
+    )
+    (image HEADER_TOP
+      (outline (path signal 381  -19989.8 -838.2  -19989.8 -685.8))
+      (outline (path signal 381  -19989.8 -939.8  -19989.8 -736.6))
+      (outline (path signal 381  19024.6 8128  19989.8 8128))
+      (outline (path signal 381  19989.8 -1270  19989.8 -685.8))
+      (outline (path signal 381  19989.8 8102.6  19989.8 7594.6))
+      (outline (path signal 381  -19989.8 8128  -19989.8 7594.6))
+      (outline (path signal 381  -19989.8 -1270  -19989.8 -838.2))
+      (outline (path signal 381  -18796 8128  -19977.1 8128))
+      (outline (path signal 381  -18961.1 -1270  -19989.8 -1270))
+      (outline (path signal 381  18986.5 -1270  19989.8 -1270))
+      (outline (path signal 381  15240 8128  19050 8128))
+      (outline (path signal 381  19050 8128  19050 7366))
+      (outline (path signal 381  -15240 8128  -19050 8128))
+      (outline (path signal 381  -19050 8128  -19050 7620))
+      (outline (path signal 381  -15240 -1270  -19050 -1270))
+      (outline (path signal 381  -19050 -1270  -19050 7620))
+      (outline (path signal 381  15240 -1270  19050 -1270))
+      (outline (path signal 381  19050 -1270  19050 7620))
+      (outline (path signal 381  15240 -1270  -15240 -1270))
+      (outline (path signal 381  -15240 8128  15240 8128))
+      (pin Rect[A]Pad_1524x1524_um 1 -17780 0)
+      (pin Round[A]Pad_1524_um 2 -15240 0)
+      (pin Round[A]Pad_1524_um 3 -12700 0)
+      (pin Round[A]Pad_1524_um 4 -10160 0)
+      (pin Round[A]Pad_1524_um 5 -7620 0)
+      (pin Round[A]Pad_1524_um 6 -5080 0)
+      (pin Round[A]Pad_1524_um 7 -2540 0)
+      (pin Round[A]Pad_1524_um 8 0 0)
+      (pin Round[A]Pad_1524_um 9 2540 0)
+      (pin Round[A]Pad_1524_um 10 5080 0)
+      (pin Round[A]Pad_1524_um 11 7620 0)
+      (pin Round[A]Pad_1524_um 12 10160 0)
+      (pin Round[A]Pad_1524_um 13 12700 0)
+      (pin Round[A]Pad_1524_um 14 15240 0)
+      (pin Round[A]Pad_1524_um 15 17780 0)
+    )
+    (image MOUNT_HOLE_4_40
+      (pin Round[A]Pad_3302_um @1 0 0)
+    )
+    (padstack Round[A]Pad_1524_um
+      (shape (circle F.Cu 1524))
+      (shape (circle B.Cu 1524))
+      (attach off)
+    )